Power Management Architect for High-Performance RISC-V SoCs
SiFive
SiFive is seeking a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer to design PM, reset and clocking solutions for RISC-V CPU and SoC IP. You will work in a fast-paced team turning hardware into highly configurable IP. You will collaborate with architecture, design verification, and software teams to meet frequency, area and power goals, with a focus on DVFS, DFT, and RTL quality checks. BS/MS in EE/CE/CS preferred. #J-18808-Ljbffr SiFive
Vacancy posted 1 day ago
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