Lead, Physical Design & STA for FPGA SoCs
191 Altera Corporation
Altera seeks an experienced Physical Design Implementation & STA Lead to drive high-quality physical implementation and timing closure for next-generation FPGA SoCs. You will lead block-level implementation, CTS, ECOs, and signoff activities, coordinating with RTL, CAD, DFT, and library teams. This senior role involves project leadership and mentoring, with emphasis on ML/AI-assisted design methodologies, timing constraints, and robust signoff processes. #J-18808-Ljbffr 191 Altera Corporation
Vacancy posted 9 hours ago
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