Analog Layout Automation Engineer

Join Apples Silicon Engineering Group (SEG) and be at the forefront of shaping the next generation of Apples systems-on-chip (SOCs)! Our SOCs featuring multi-billion transistors are the heart of iconic devices like iPhones iPads and Macs. Were seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits covering SerDes PLLs and sensors with a focus on automation and leveraging AI/ML techniques for improved design and efficiency.

As an Analog Layout Automation Engineer youll convert design concepts into silicon by collaborating with circuit designers and using advanced including AI-powered CAD tools to create high-performance analog and mixed-signal layouts. You will review floor plans analyze circuits run verification suites and resolve LVS/DRC/ERC issues to deliver next-generation SOCs. Youll also drive automation by developing scripts improving workflows and applying AI/ML for layout optimization verification acceleration advanced modeling intelligent quality metrics reduced manual effort and data-driven design insights.

BS and a minimum of 10 years relevant industry experience.

Experience designing analog and mixed-signal layouts in deep-submicron CMOS and FinFET programming/scripting skills in SKILL Perl TCL Shell and/or Python with emphasis on layout automation productivity tooling and data understanding of supervised and self-supervised learning convolutional neural networks (CNNs) and core training concepts such as loss functions backpropagation and -on experience with PyTorch for model development and ability to automate layout tasks flows and quality checks using scripting and CAD record in implementing high-quality analog layouts with tight device matching low noise and low power with failure-prone circuit/layout structures analog and DFM best practices and the ability to diagnose and resolve layout-related proficiency in custom and standard-cell floor planning hierarchical layout assembly and physical of image processing fundamentals spatial representations multi-channel image handling segmentation and object detection understanding of IR drop RC delay electromigration self-heating coupling capacitance and related reliability proficiency in interpreting physical verification reports including DRC ERC and using advanced Cadence Virtuoso features (XL EAD APR Constraint Manager) and familiarity with Cadence with CAD automation workflows and PCell communication skills and the ability to work effectively with cross-functional teams.

Required Experience:

IC