HBM SoC Physical Design Engineer for PPA & Tapeout
Micron Technology
Micron Technology in San Francisco, CA, is seeking a hands-on SoC Physical Design Engineer to drive implementation from netlist through GDSII for advanced memory/SoC products. You will partner with RTL, verification, IP, packaging and manufacturing teams to meet stringent PPA targets and signoff criteria. Ideal candidates have tapeout experience on cutting‑edge nodes, strong scripting skills (Python/TCL), and deep knowledge of UPF/CPF power delivery. #J-18808-Ljbffr Micron Technology
Vacancy posted 1 day ago
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