Lead ASIC DFT Engineer

Seeking a full-time remote Lead ASIC DFT Engineer with over 10 years of experience to manage DFT architecture, implementation, and verification for complex ASIC and SoC designs while working PST hours. Key responsibilities Lead DFT architecture and implementation, ensuring effective verification and fault coverage closure Oversee ATPG pattern generation and silicon bring-up, collaborating with cross-functional teams for debugging efforts Utilize scripting skills in TCL, Perl, or Python to enhance DFT processes and manage large SoC designs Required qualifications 10+ years of experience in ASIC DFT Engineering Strong expertise in Scan, ATPG, MBIST/LBIST, JTAG, and Boundary Scan Proficiency in tools such as Synopsys DFTMax, TetraMAX, and Tessent Experience with timing simulations, silicon debug, and post-silicon validation Familiarity with pattern retargeting/porting and DFT sign-off processes