Senior ASIC Verification Engineer
Experis/Manpower Group
Our client is seeking a Senior ASIC Verification Engineer to join their team. As a Senior ASIC Verification Engineer, you will be part of the engineering organization supporting the DFT and ASIC verification efforts for next-generation coherent optical communications products. The ideal candidate will be motivated , proactive , and intellectually curious , with a strong focus on Design-for-Test (DFT) and silicon validation.
Job Title: Senior ASIC Verification Engineer Location: San Jose, California (Onsite) Pay Range: $50 - $55/hr on W2 What's the Job?- Lead implementation of SSN-based test flow DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, using Siemens Tessent tools for RTL and gate netlist DFT implementation.
- Generate and deliver ATPG test patterns for stuck-at, transition, cell-aware, and path delay fault models; drive scan-based diagnosis methodology for silicon failure debug; and support post-silicon testing and validation.
- Evaluate design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools to ensure DFT feasibility and readiness.
- Integrate and verify DFT fabrics and IP within subsystems, ensuring correct connectivity, behavior, and test coverage alignment.
- Run simulations and debug issues for non-timing and back-annotated timing (SDF) gate-level simulations; develop test scripts and automate processes using Python, Tcl, or C++.
- Bachelors + 8 years of related experience, or Masters + 6 years of related experience, or PhD + 3 years of related experience.
- Prior experience working with ASICs, including scan insertion and DFT setup, integration, and validation.
- Prior experience implementing DFT architectures, including scan insertion, compression/decompression logic, and memory/logic BIST.
- Strong RTL experience to understand and debug issues related to DFT, including clocking considerations and complex integration challenges.
- Experience with Verilog/SystemVerilog and the ability to solve complex problems such as clock domain crossings; familiarity with advanced silicon process and technology nodes for high-speed, low-power designs.
- Opportunity to lead DFT solution development for multi-100G to 1.6T coherent optical communications products.
- Hands-on ownership of ATPG pattern generation, silicon failure debug, and post-silicon validation support.
- Use of industry-standard Siemens Tessent workflows for RTL and gate netlist DFT implementation.
- Collaboration across subsystem integration and verification to ensure DFT fabrics and IP are correctly deployed.
- A role built for problem-solvers who enjoy automation, simulation/debug, and continuous improvement.
- Medical and Prescription Drug Plans
- Dental Plan
- Vision Plan
- Health Savings Account
- Health Flexible Spending Account
- Dependent Care Flexible Spending Account
- Supplemental Life Insurance
- Short Term and Long Term Disability Insurance
- Business Travel Insurance
- 401(k), Plus Match
- Weekly Pay
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- Possible 3 Month CTH | No Fees | Do Not Re-Post | Confidential
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