SoC Power Modeling Engineer

Do you have a passion for crafting new solutions? As part of our Silicon Engineering group, you will generate ideas and turn them into reality. You will be part of the team responsible for designing state‑of‑the‑art ASICs that are integral to many Apple products. We are looking for an engineer who will work on the modeling of power dissipation of various IPs including AI/ML and the corresponding power rails, peak current requirements and voltage‑frequency operating points for upcoming generations of Apple SOCs. This role provides an opportunity to participate in optimization of a variety of leading edge chips for power‑efficiency. You will collaborate across many teams including architecture, design, thermals, PMIC and system design to model power and current profiles for various IPs of the SOC, and the voltages‑frequency operating points. The job also involves partnering with the lab and silicon characterization/validation and technology teams on correlating the models to the HW data. Responsibilities Model power dissipation and power delivery. Establish voltages for DVFM states of IPs, including Neural Engines, CPUs, Graphics, compute (AI/ML) accelerators, media IPs, caches and fabric. Model power dissipation for customer use‑cases. Interact with the Technology team, Silicon Validation, and Product Engineering teams to establish voltage‑frequency design points pre‑and post‑silicon. Work with the power lab and test teams to correlate models to HW data. Minimum Qualifications A minimum of a bachelor’s degree in relevant field and a minimum of 10 years of relevant industry experience. Preferred Qualifications Our ideal candidate should have 3+ years relevant experience, programming skills and an understanding of low‑power digital design and power fundamentals. Understanding of SOC power modeling and current demand. Understanding of electrical properties of on‑die PDN, power gating, package and system power delivery. Skills in scripting, data analysis and experience with EDA tools. Understanding of VLSI design flow and CMOS technology. Extensive background in EE. Ability to understand and model thermal control loops and throttling mechanisms. Familiarity with physical design tools for power optimization. Great teammate and excellent communication skills. Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant. #J-18808-Ljbffr Apple Inc.