Principal Signal Integrity Engineer (Santa Clara)

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration.We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI. About the RoleAs the Senior Staff SI/PI Engineer, you will be the technical authority responsible for the electrical integrity of d-Matrix’s high-performance AI compute platforms. In an environment where we are pushing 112G/224G SerDes and delivering thousands of Amps to multi-chip modules (MCM), your role is critical to ensuring that our Digital In-Memory Computing architecture translates into stable, manufacturable, and world-class hardware.You will lead the end-to-end modeling, simulation, and correlation efforts—from the silicon die through the package and across the system PCBA.Key Responsibilities• End-to-End SI/PI Ownership: Drive the SI/PI strategy for next-generation AI accelerators, focusing on high-speed interfaces (PCIe Gen6/7, CXL, LPDDR5) and custom Chiplet-to-Chiplet interconnects.• MCM & Package Simulation: Lead the modeling and analysis of complex multi-chip packages, including interposer routing, micro-bump parasitic extraction, and die-to-die (D2D) link budgeting.• Advanced PDN Architecting: Design and optimize the Power Delivery Network (PDN) to meet stringent Z_Target requirements. Perform transient analysis to ensure voltage stability during massive AI workload swings.• Link Analysis & Budgeting: Perform comprehensive channel simulations (pre- and post-layout) using IBIS-AMI models. Define jitter, crosstalk, and loss budgets (insertion/return loss) for 112G+ channels.• Lab Correlation & Measurement: Lead the Gold Suite validation in the lab. Correlate simulation results with VNA, TDR, and high-speed oscilloscope measurements to close the loop on design accuracy.• Constraint Management: Translate complex simulation findings into actionable physical layout constraints for the PCB Design team, specifically for advanced stack-ups and high-density routing.• Technical Mentorship: Act as the subject matter expert, guiding hardware and layout engineers on SI/PI best practices and state-of-the-art mitigation techniques (e.g., skip-vias, voiding, material selection).Required Qualifications• Education: MS/PhD in Electrical Engineering or a related field with a focus on Electromagnetics or Signal Integrity.• Experience: 12+ years in SI/PI design for high-performance networking, GPUs, or server platforms.• Simulation Mastery: Expert-level proficiency in industry-standard tools:o SI: Ansys HFSS, Cadence Sigrity, Keysight ADS, or Simbeor.o PI: Ansys SIwave, Cadence PowerSI, or CST.• High-Speed Expertise: Proven track record with 112G SerDes and high-speed memory architectures. Deep understanding of PAM4 signaling and FEC (Forward Error Correction) impact on link margins.• Measurement Skills: Hands-on experience with 50GHz+ VNAs, TDRs, and real-time/sampling oscilloscopes.Preferred Skills• Knowledge of PCB Material Science (e.g., glass weave effects, skin effect loss, copper roughness modeling).• Experience with Python or MATLAB for post-processing large simulation datasets and automating sweep analysis.• Familiarity with OCP (Open Compute Project) hardware specifications for AI modules.Equal Opportunity Employment Policyd-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation. Compensation Range: $175K - $265KLocationSanta ClaraEmployment TypeFull timeLocation TypeHybridDepartmentSystems EngineeringCompensationL5$175K – $265KThe pay range below is for all roles at this level across all US locations and functions. Individual pay rates depend on a number of factors—including the role’s function and location, as well as the individual’s knowledge, skills, experience, education, and training. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours.