Sign up to access all features of our service.
  • Job search
  • Favorites
  • Create a CV
    New
  • Salaries
  • Subscriptions

PLL Design Engineer - Frequency Synthesis & Clocking

Apple Inc.

Apple Inc. seeks a skilled engineer to develop cutting-edge frequency synthesizers across Compute, SoC, SerDes, and cellular platforms. You will contribute to Apple’s leadership in innovation and influence market presence with your expertise in PLL/FLL and clocking dynamics. You will work within the Analog‑Mixed/Signal group to push design boundaries, solve complex problems, and deliver high‑quality hard IPs on tight production schedules. A proactive, collaborative mindset is essential. #J-18808-Ljbffr Apple Inc.

Vacancy posted 3 days ago
Similar jobs that could be interesting for youBased on the PLL Design Engineer - Frequency Synthesis & Clocking in Austin, TX vacancy
  • $141.91k - $269.1k

     ...are looking for a Senior Clock Architecture & Design Engineer a pivotal role in developing...  ...networks for high-frequency flagship CPU designsPioneer...  ...optimize advanced clock tree synthesis flows for complex, multi-billion...  ...in clocking architecture, PLL/DLL architecture and... 
    Suggested
    Full time
    Local area
    Immediate start
    Worldwide
    Shift work

    Intel

    Austin, TX
    2 days ago
  •  ...escalating complexity of SOC/PHY designs and multiplying projects...  ...to develop cutting‑edge frequency synthesizers for a variety...  ...proficiency in PLL/FLL and frequency synthesis architecture and circuit design...  ...compensation techniques. Clocking Mastery: Deep understanding... 
    Suggested

    Apple Inc.

    Austin, TX
    3 days ago
  • $136k - $218.5k

    The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible for crafting all aspects...  ...team collaborates with the front design team to understand the clocking...  ...Verilog), verification and logic synthesis.Strong coding skills in python or... 
    Suggested
    Full time
    Work experience placement

    Nvidia

    Austin, TX
    3 days ago
  • $143.15k - $265.85k

    Staff Digital Design Engineer - SOC Low Power, Clocking & Integration (Austin, TX) Responsibilities The Role as a Staff Digital Design Engineer, you will...  ...issues identified during simulation, emulation, synthesis, and silicon bring‑up Architect and integrate SoC interconnects... 
    Suggested
    Flexible hours
    Shift work

    Silicon Laboratories Inc.

    Austin, TX
    3 days ago
  • $141.91k - $269.1k

     ...will have a front seat in designing the latest core IP to...  ...physical design flow including synthesis, place and route, clock tree synthesis, floor...  ...parameters such as power, frequency, and area. Participates in...  ...:Bachelors in Computer Engineering or Electrical Engineering... 
    Suggested
    Full time
    Work experience placement
    Internship
    Local area
    Immediate start
    Shift work

    Intel

    Austin, TX
    1 day ago
  • $100k

     ...Tenstorrent is seeking talented Physical Design Engineers to implement high-performance...  ...complete implementation flow from synthesis to tapeout, working alongside...  ...LVS, EM/IR, LEC/Formality), multi-clock/CDC-aware implementation, PLL/DLL integration, and DFT-aware physical... 
    Permanent employment

    Tenstorrent

    Austin, TX
    13 hours ago
  • $136k - $218.5k

     ...motivated Senior ASIC Physical Design Engineer, Netlisting to join our...  ...drive physical design of high-frequency and low-power CPUs, GPUs, SoCs...  ...asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc.Help... 
    Full time
    Shift work

    Nvidia

    Austin, TX
    13 hours ago
  • $136k - $218.5k

     ...motivated Senior Physical Design and Timing Engineer to join our dynamic and growing...  ...design and timing of high-frequency and low-power NVIDIA CPUs,...  ...RTL to gds2, including synthesis, equivalence checking, floor...  ...floorplanning, placement, clock-tree synthesis, routing, physical... 
    Full time

    Nvidia

    Austin, TX
    1 day ago
  • $164.47k - $269.1k

     ...and ImpactAs a Senior CPU Physical Design Engineer, you will play a critical role in delivering...  ...flow, including floor planning, synthesis, place and route, clock tree synthesis, static timing...  ...microarchitectures for power, area, and frequency improvements.Build and refine... 
    Full time
    Local area
    Immediate start
    Worldwide
    Shift work

    Intel

    Austin, TX
    1 day ago
  • $256.05k - $361.48k

     ...delighting our customers.The Physical Design Integration Engineer performs physical design...  ...CPU physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static...  ...parameters such as power, frequency, and area. Participates in the development... 
    Full time
    Work experience placement
    Local area
    Immediate start
    Flexible hours
    Shift work

    Intel

    Austin, TX
    1 day ago
  • A pioneering tech company in Austin, Texas, is seeking a Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer. This role involves designing industry-leading CPU cores and subsystems focused on RISC-V technology. The ideal candidate will have over 3 years... 
    Flexible hours

    SiFive

    Austin, TX
    3 days ago
  • $178.85k - $218.59k

     ...every market segment of chip design, including artificial intelligence...  ...is looking for hardware engineers who are passionate about designing...  ....As a Power-Management/Reset/Clock Micro-Architect and RTL...  ...optimise physical design to meet frequency, area, power goals.Work with... 
    Full time
    Work experience placement
    Flexible hours

    SiFive

    Austin, TX
    4 days ago
  • $164.47k - $269.1k

     ...: About the RoleJoin Intel’s CPU Design Team within the Silicon & Platform Engineering (SPE) Group, where you will help...  ...architecturesDesign and validate multi-clock domain and CDC...  ...features, including:Dynamic voltage and frequency scaling (DVFS)Power/thermal managementReset... 
    Full time
    Local area
    Immediate start
    Shift work

    Intel

    Austin, TX
    1 day ago
  • $140k - $229.8k

    Company:Qualcomm Technologies, Inc.Job Area:Engineering Group, Engineering Group > ASICS...  ...seeking candidates for several physical design engineering positions in our SOC and...  ...placement, multi-mode & multi-corner (MMMC) clock tree synthesis, routing, timing optimization and... 
    Work experience placement
    Work from home

    Qualcomm

    Austin, TX
    4 days ago
  • $116k - $189.75k

     ...System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You will focus...  ...to ensure design quality (e.g., cross clock domains (CDC), clocks, reset, latency,...  ...verification tools (dc_shell or equivalent synthesis tools, VCS or equivalent simulation... 
    Full time

    Nvidia

    Austin, TX
    4 days ago
  • $141.91k - $269.1k

     ...Valley. No one else is obsessed with engineering and has a brighter future. Every...  ...Role and Impact:As a CPU Logic Design Engineer, you will play a...  ...including techniques applicable to high-frequency optimization.5+ years experience in Cross-clock domain crossings and power aware... 
    Full time
    Internship
    Local area
    Immediate start
    Shift work

    Intel

    Austin, TX
    4 days ago
  •  ...has been propelled by the top engineers in mixed-signal processing....  ...looking for an expert Physical Design Engineer to join its...  ...from RTL to GDSII.Perform RTL synthesis and scan stitching.Apply deep...  ...floor plan.You will analyze clock distribution on full-chip assembly... 
    Full time
    Work at office
    Relocation

    Cirrus Logic

    Austin, TX
    4 days ago
  •  ...your career. THE ROLE:As a CPU Core RTL Design Engineer, you will help design and optimize next...  ...design verification, synthesis, timing closure, and physical design effortsDebug...  ...Python, Tcl), and concepts such as DFT, clocking, reset, and power managementACADEMIC CREDENTIALS... 

    AMD

    Austin, TX
    13 hours ago
  • $168k - $264.5k

    We are looking for a Senior CPU Design Engineer! NVIDIA is seeking best-in-class CPU Design Engineers...  ..., timing and power targets. Deliver a synthesis/timing clean design while working with...  ...including chip floor plan, power/clock distribution, chip assembly, timing closure... 
    Full time
    Remote work

    Nvidia

    Austin, TX
    4 days ago
  • $100k

     ...are set as much by flow maturity as by design work. This role develops, deploys, and...  ...physical design or CAD methodology engineer who has built flows that production teams...  ..., low-power intent (UPF/CPF), clock tree synthesis, and signoff (EM/IR, DRC/LVS).Experience... 
    Permanent employment

    Tenstorrent

    Austin, TX
    3 days ago
  • $116k - $189.75k

    NVIDIA is looking for an SOC Design Engineer with proven hardware design and methodology expertise...  ...in ASIC verification.Knowledge of Clocks/Resets design and verification.Exposure...  ...verification flows.Exposure to backend flows (Synthesis, Timing, etc).NVIDIA is widely... 
    Full time

    Nvidia

    Austin, TX
    4 days ago
  •  ...has been propelled by the top engineers in mixed-signal processing....  ...grow your career! As a Digital Design Engineer, you will be part of...  ...and RTL development. Clock and reset domain crossing.Functional...  ...verification. Timing constraints and synthesis. Experience designing and... 
    Full time

    Cirrus Logic

    Austin, TX
    4 days ago
  •  ...join the high-performance core physical design team with the charter to own a portion of the core in which you will start with Synthesis and deliver a Placed and Routed design that...  ...in one of many functional areas (e.g., clocks, standard cell libraries, synthesis, place... 

    AMD

    Austin, TX
    13 hours ago
  •  ...of enabling human life on Mars.SR. RTL DESIGN ENGINEER (SILICON ENGINEERING)At SpaceX we’re leveraging...  ...level and deliver the fully verified, synthesis/timing clean designWork closely with...  ...to solve complex problems including clock domain crossings and power... 
    Permanent employment
    Worldwide
    Weekend work

    SpaceX

    Austin, TX
    1 day ago
  • $100k

     ...implementation of those IP blocks end to end, from synthesis through PnR, timing closure, and GDSII...  ...posting.Who You AreA hands-on physical design engineer who owns blocks end to end, with a...  ..., power grids, pin placement, and clocking strategies, and delivering IP... 
    Permanent employment

    Tenstorrent

    Austin, TX
    4 days ago
  • $183k - $247.6k

    Annapurna Labs designs silicon and software that accelerates innovation...  ...for an ASIC Physical Design Engineer to help us trail-blaze new...  ...implementation through synthesis, floor planning, bus / pin planning...  ..., place and route, power/clock distribution, congestion analysis... 
    Local area
    Flexible hours

    Amazon

    Austin, TX
    13 hours ago
  • GPU Physical Verification Design Engineer Do you love creating elegant solutions to highly complex...  ...Design topics: multiple voltage and clock domains, ESD solutions, and mixed...  ...large subsystem designs (>20M gates) with frequencies in excess of 1GHz applying brand new technologies... 

    Apple Inc.

    Austin, TX
    3 days ago
  •  ...advanced solutions across chip design markets, including artificial...  ...is looking for hardware engineers who are passionate about designing...  ...As a Power-Management/Reset/Clock Micro-Architect and RTL...  ...implementation team to meet frequency, area, and power goals. Work... 
    Flexible hours

    SiFive

    Austin, TX
    3 days ago
  •  ...of technology.Experienced Millimeter-Wave (mmWave) IC designer specialize in engineering high-frequency (30 GHz+) transceivers and components for 5G/6G communications...  ...range and power efficiency. Deep experience in RF PLL design including Sigma delta, FRAC-N PLL. Phase noise... 
    Full time

    Cadence Design Systems

    Austin, TX
    3 days ago
  • OverviewThe Arm Solutions Engineering Security IP Team is seeking creative...  ...Security Hardware Designers to join our team. This is a fantastic...  ...architecture including multi-clock domains, AXI/AHB protocols,...  ...architectures.Competency with synthesis, timing analysis, constraints... 
    Work at office
    Local area
    Relocation

    ARM

    Austin, TX
    13 hours ago

Do you want to receive more vacancies?

Subscribe and receive similar vacancies to PLL Design Engineer - Frequency Synthesis & Clocking. Be the first to apply!