Director, Physical Design Engineering

President at SBT | 19 years of advising leaders at semiconductor and deep tech companies | Architecting teams from startups to F500 organizations Company Overview This confidential client is strategically bringing on a Director of Physical Design Engineering to build and lead a PD organization from the ground up. This is a highly technical, hands‑on leadership role responsible for architecting physical implementation strategy, driving execution across complex SoCs, and shaping the long‑term direction of the company’s chip development efforts. The Director will collaborate cross‑functionally with systems hardware teams, software architects, and executive leadership while guiding a growing team through the full lifecycle of advanced semiconductor development. Responsibilities Provide hands‑on technical leadership across complex physical design activities, including clock/reset architecture, power delivery networks, floorplanning, routing strategies, and interconnect topology development. Drive end‑to‑end physical implementation—from synthesis, floorplanning, power planning, and place‑and‑route through timing closure, physical verification, and final tapeout. Build and scale a Physical Design organization from scratch, including hiring, mentoring, establishing methodologies, and defining best‑in‑class PD workflows. Partner with architects and micro‑architects to define, explore, and construct major physical structures at block, cluster, and top levels. Collaborate closely with cross‑functional teams to ensure seamless product execution and successful high‑volume silicon readiness. Qualifications 10+ years of industry experience in Physical Design engineering, with deep expertise across full‑chip implementation, advanced nodes, multi‑IP integration, timing closure, and tapeout signoff. 5+ years of leadership experience, including building and leading Physical Design teams or organizations. Demonstrated success owning top‑level floorplanning, clock/power distribution, physical verification, and large‑scale P&R implementation. Strong experience collaborating with architecture, RTL design, packaging, and system teams on complex SoC programs. Experience with DSP‑based chip architectures is a strong preference. This role is remote with occasional travel to the on‑site location. Seniority level Director Employment type Full‑time Job function Semiconductor Manufacturing and Computer Hardware Manufacturing #J-18808-Ljbffr