Lead SoC Architect

Job Title: Lead SoC ArchitectJob Location: San Francisco, CA or Los Altos, CA - hybridCompensation: $300K - $425K base DOE plus equityRequirements: SoC Architecture, ARM Architecture, Advanced Nodes, AMBA Protocols (CHI, AXI, ACE, APB), CPU/GPU/NPU, HPC / Edge AI SoCWe're a well-funded, stealth startup building a next-generation, end-to-end computing platform powered by a custom, high-performance edge SoC on an advanced process node. By integrating flagship compute IP into an industry-leading design, we are building the optimized silicon foundation for our software platform from the ground up.We're building a tight-knit, experienced in-house team to drive engineering outcomes and partner with a Tier-1 ASIC design house through the process. As our Lead SoC Architect, you will own the top-level system architecture, shaping the blueprint of our silicon and providing technical direction for both our core engineering team and external partners.Position OverviewWe are seeking a Lead SoC Architect to define and drive the architecture of next-generation system-on-chip products. The role is responsible for developing system-level architectures and interfaces, selecting and integrating IP (CPU, GPU, NPU and peripheral blocks), defining interconnect and memory subsystems, and delivering scalable, power- and performance-optimized SoC solutions. The Lead SoC Architect will lead cross-functional technical teams, work with silicon and IP partners, and guide implementation from specification through silicon bring-up.Key ResponsibilitiesOwn the SoC Architecture: Own the overall SoC architecture, translating product requirements into executable engineering blueprint, and ensure our implementation partner's frontend team is setting the right bar.Drive System Integration: Collaborate seamlessly with the team to integrate compute, fabric, SerDes, etc.Manage Architectural Trade-offs: Take a data-driven approach to finding the balance between thermal constraints, performance goals, and power efficiency.Guide Execution: Serve as the primary technical bridge to our ASIC partner. You will actively audit their floorplanning, timing closure, and routing strategies to ensure the physical implementation preserves our architectural intent.QualificationsBachelors or Masters degree in Electrical Engineering, Computer Engineering, Computer Science or related field; advanced degree preferred.10+ years of SoC architecture or system-level design experience with a proven track record of shipping silicon and successful tapeouts on advanced nodes.Deep expertise with SoC architecture principles including ARM-based CPU platforms and AMBA protocols.Hands-on experience and strong knowledge of interconnect and coherence protocols: AXI, ACE, CHI and NoC design and trade-offs.Practical experience integrating CPU, GPU and ML accelerators (NPU), and designing for heterogeneous compute.Experience with memory subsystems and DDR interfaces, caching strategies and system-level performance optimization.Familiarity with high-speed interfaces and standards such as PCIe and UCIe, and experience architecting die-to-die connectivity.Strong system-level thinking, performance/power modeling skills and architecture documentation experience.Excellent leadership, communication and collaboration skills with experience leading cross-functional teams and interacting with IP/partner ecosystems.Experience with RTL, firmware bring-up, silicon validation and production tape-out processes is highly desirable.#EnghpBenefitsMedical/Dental/Vision benefitsVacation/PTO401KEquityFlexible Work Arrangements