Senior Principal System Validation Engineer

Senior Principal System Validation Engineer San Jose, CA Astera Labs (NASDAQ: ALAB)provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL, Ethernet, PCIe, and UALink semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at Job Description Develop and perform system validation tests using leading-edge Data Center equipment and scalable automation platforms. The validation team holds customers’ system requirements in the highest regard and is solely responsible for certifying a product’s conformance to this high bar. Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs’ game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. Formulate a comprehensive validation plan, automate the testing of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior, report results and specification compliance in an automated fashion. Work with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs’ solutions. Strong academic and technical background in Electrical or Computer Engineering. At a minimum, a Bachelor’s is required, and a Master’s is preferred. ≥12 years\' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. Basic understanding of x86/ARM architecture, UEFI/Linux boot sequence. Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer/internal meetings in advance, and to work with minimal guidance and supervision. Entrepreneurial, open-mind behavior and can-do attitude. Think and act with the customer in mind! Required experience Hands-on, thorough knowledge of high-speed protocols like CXL, PCIe, NVMe, or Ethernet. Experience with Silicon/System bring-up, validation, and debug experience, including in customer systems. A strong background in developing bench automation techniques, especially using Python,with emphasis onexecution efficiency, repeatability, data analysis and reporting. Experience with lab equipment including protocol analyzers, in-circuit debuggers, and CPU-based tool suites. Preferred experience Working knowledge of C or C++ for embedded FW and device drivers. Working knowledge of SerDes architecture including Tx/Rx equalization, adaptation, CDR, block level requirements and SerDes link jitter budget. Experience with PAM4 SerDes is a huge bonus! Familiarity with PCIe compliance standards and ability to follow and be involved in compliance consortiums to adapt the tests to be run from X86/ARM based platforms. Knowledge of schematic capture and PCB layout tools from Cadence Allegro, Altium, etc. Knowledge of simulation tools such as Keysight ADS, Mathworks QCD, etc. for IBIS-AMI analysis. The base salary range is $184,000.00 USD – $260,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities. EEO Statement We are an equal opportunity employer and value diversity. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or protected veteran status. #J-18808-Ljbffr