Senior Physical Design Methodology Engineer, PPA Improvement Technology Scaling

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in an inclusive, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer(s) - PPA Improvement Technology Scaling to join our outstanding Methodology team. Come and take a part in crafting our groundbreaking and innovating chips, enjoy working in a meaningful, growing and professional environment where you make a significant impact in a technology-focused company.What you'll be doing:Developing physical design methodologies for implementation of graphics processors and SOCs.Key responsibility includes developing unique and creative solutions to the state of the art physical design problems that are needed for NVIDIA chips.Participate in PPA experiments for testing and developing new technologies for CPUs/GPUs including running chip floorplan, power and clock distribution, chip assembly and P&R, timing analysis and closure, power and noise analysis and back-end verification across multiple projects.Develop Automation to solve early design collaterals, for eg. developing scripts for analysis of new library cells, scripts for modifying design constraints for new technologiesWhat we need to see:MS in Electrical or Computer Engineering (or equivalent experience)Minimum 5 years’ experience in Physical Design EngineeringFamiliar with aspects of chip design including Floor planning, Clock and Power distribution, Place and Route, Integration and Verification.Experience with Physical Design related to CPU designs is a plusStrong background with hierarchical design approach, top-down design, budgeting, timing and physical convergence.Familiar with various process related design issues including Design for Yield and Manufacturability, EM and IR closure and thermal management.You'll need to have expertise and in-depth knowledge of industry standard EDA tools.Proficiency in programming and scripting languages, such as, Perl, Python, and C++.NVIDIA is widely considered to be the leader of AI computing, and one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you!Widely considered to be one of the technology world’s most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.You will also be eligible for equity and benefits.Applications for this job will be accepted at least until November 1, 2026.This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes.NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.SummaryLocation: US, CA, Santa Clara; US, TX, AustinType: Full time