Senior Photonics Test Engineer
$126.89k - $166.13kEntangled Future
Senior Photonics Test Engineer at IonQ, Boston, Massachusetts, United States. A senior-level full time position in the Research & Development team, listed under hardware engineering. The Role We are looking for a Senior Photonics Test Engineer to join our Quantum Interconnect Division. As a Senior Photonics Test Engineer, you’ll be part of a cross-functional team whose mission is to lead IonQ on its journey to build the world’s best quantum computers to solve the world’s most complex problems. In this role, you will be responsible for the characterization and test development of on-chip photonic devices. The ideal candidate is someone who is a detail-oriented problem solver with strong teamwork skills. The approximate base salary range for this position is $126,887 - $166,127 . The total compensation package includes base, bonus, equity, and a range of benefit options found on our career site. Compensation will vary based on individual factors such as education, qualifications, and experience of the final candidate(s), specific office location, and calibration against relevant market data and internal team equity. Posted base salary figures are subject to change as new market data becomes available. Our benefits include comprehensive medical, dental, and vision plans, matching 401(k), unlimited PTO and paid holidays, parental/adoption leave, legal insurance, and a home technology stipend. Details of participation in these benefit plans will be provided when a candidate receives an offer of employment. At IonQ, we believe in fair treatment, access, opportunity, and advancement for all while striving to identify and eliminate barriers. We empower employees to thrive by fostering a culture of autonomy, productivity, and respect. We are dedicated to creating an environment where individuals can feel welcomed, respected, supported, and valued. US Technical Jobs. The position you are applying for will require access to technology that is subject to U.S. export control and government contract restrictions. Employment with IonQ is contingent on either verifying “U.S. Person” (e.g., U.S. citizen, U.S. national, U.S. Responsibilities Design, upgrade, and expand the testing infrastructure for characterizing classical integrated photonics devices and components (passive and active) at chip and wafer level scale, utilizing both room-temperature and cryogenic setups. Develop and perform robust testing procedures for component-level characterization. Automate the test pipeline, including instrument setup, data acquisition, and analysis, while maintaining high-quality, scalable, and well-tested scripts. Conduct characterization using room-temperature and cryogenic setups and provide data-driven feedback to design engineers to improve component performance. Collaborate with design, packaging, and system teams to optimize testing features and develop a library of testing structures for platform improvement. Requirements 3+ years of professional experience in the hands-on characterization of PIC devices or an equivalent combination of education and experience. Master or Ph.D. in engineering or related field/discipline or equivalent practical experience. Programming experience in a general-purpose programming language (like Python, Matlab, etc.) for test automation. Experience with test instrumentation and methods for characterizing classical integrated photonics devices. Strong data processing, visualization, and organizational skills. Hands-on experience with room-temperature optical test setups Nice to Have 5+ years of design and characterization experience of classical integrated photonics devices. 3+ years of industry experience. Familiarity with free-space optics and imaging systems. Hands-on experience with cryogenic optical test setups. Experience working with laser sources and fiber components. Strong programming skills for data analysis and experimental automation software, and experience with version control systems such as git. Familiarity with fabrication processes and design constraints for PICs. #J-18808-Ljbffr
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