Staff Engineer

Design, implement, and maintain chip design build flows supporting block, subsystem, full-chip, and multi-chip simulations Develop and own build scripts and orchestration logic for compile, elaborate, simulate, and regression workflows Improve build performance through dependency analysis, incremental builds, caching, and flow optimization Define and evolve methodology standards for front-end design and verification flows Architect and enhance CI / pre-submit verification flows to improve quality and turnaround time Integrate and support industry EDA tools within robust scripted flows Collaborate with RTL, DV, methodology, and infrastructure teams Debug complex infrastructure and build-system issues Drive adoption through documentation and training Requirements Bachelor’s or Master’s degrees in electrical engineering, Computer Engineering, Computer Science, or related field 8+ years of experience in ASIC/SoC design, verification, or methodology roles Strong programming skills in Python and at least one of TCL, C/C++, or shell scripting Experience with make-based or graph-based build systems Understanding of front-end chip design flows Experience debugging large-scale infrastructure issues Familiarity with EDA toolchains Strong problem-solving and collaboration skills Core Competencies Expertise in ASIC/SoC design and verification, with strong programming skills in Python and familiarity with EDA toolchains. Proven ability to design and optimize build flows, enhance CI processes, and collaborate effectively across teams. Highest-signal resume keywords ASIC/SoC Design Python Programming Build System Optimization EDA Toolchain Integration Collaboration Skills ATS Optimization Keywords Hard Skills Python TCL C/C++ Shell Scripting Build Scripts Dependency Analysis Incremental Builds Flow Optimization Front-End Design Flows Debugging Infrastructure Issues Soft Skills Problem-Solving Collaboration Certifications & Qualifications Bachelor’s Degree in Electrical Engineering Master’s Degree in Electrical Engineering Industry Keywords Chip Design Verification Flows Methodology Standards Simulation Regression Workflows Tools & Technologies EDA Tools CI Tools Build Systems #J-18808-Ljbffr