Senior Digital-AMS RTL & Lab Integration Engineer
NXP Semiconductors
NXP Semiconductors in California seeks a Senior Digital/AMS Design Engineer to drive RTL design and integration for automotive SerDes transceivers. You will own the RTL path through timing closure and support lab validation of the digital-analog wrapper.
HDL proficiency (SystemVerilog/Verilog), timing analysis, CDC handling, and Python or Perl scripting are required. You will work with analog front-ends and the verification team to ensure robust operation across PVT variations.
#J-18808-LjbffrVacancy posted 2 days ago
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