Senior Software Engineer- AI for RTL Design & Formal Verification San Jose, California, United States

Senior Software Engineer- AI for RTL Design & Formal Verification

San Jose, California, United States

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at .

Senior Software Engineer – AI for RTL Design & Formal Verification

Join Astera Labs' AppliedAI organization, where we're building the connectivity infrastructure that powers AI and cloud data centers. Our team sits at the intersection ofdigital and analogdesign, verification, and AI tooling, tackling the complexity of next-generation semiconductor products at the pace our industry demands. We're lookingto develop and deploy AI-driven agents that accelerate RTL and physical design, static analysis, and formal verification workflows. The ideal candidate combines a strong ASIC and software engineering background with hands-on exposure to digital or analog design or verification, and is excited to apply LLMs and agentic systems to real chip design problems.

What You'll Be Doing

Design, develop, and deploy AI applications using LLMs, agentic frameworks, and related technologies to support RTL, physical and analog design, static/lint checking, and formal verification flows.Build infrastructure to deploy LLM-powered engineering assistants and multi-turn dialogue systems that help designers and verification engineers debug faster and close coverage sooner.Develop agentic AI solutions for tasks such as RTL rule and lint checking, RTL optimization, bug triage, formal proof convergence, and static verification report analysis; fine-tune and integrate these solutions with existing CAD/EDA flows. Build and maintain design databases and dashboards that combine agentic and deterministic retrieval to surface relevant engineering data and speed up design closure.Collaborate closely with RTL design, DV, formal verification, and CAD/EDA teams to understand pain points and translate them into AI-assisted tooling.

Basic Qualifications

• Bachelor's, Master's degree in Electrical Engineering, Computer Science/Engineering, or equivalent experience.
• 4-10 years of industry experience in software engineering, with direct exposure to RTL design, static/lint verification, or formal verification methodologies.
• Proficiency in Python for rapid prototyping, with strong fundamentals in data structures, algorithms, and software engineering practices.
• Experience with LLMs, including fine-tuning, building multi-agent systems, RAG pipelines, and vector databases.
• Familiarity with RTL design languages (Verilog/SystemVerilog) and formal/static verification tools (e.g., JasperGold, VC Formal, or similar) is strongly preferred.
• Strong analytical, communication, and interpersonal skills, with a proven ability to work effectively in a fast-paced, cross-functional startup environment.
• A proactive, self-directed approach to problem-solving and comfort operating with ambiguity.

Ways to Stand Out

• Direct experience applying AI/ML techniques to EDA or CAD flow problems.
• Proficiency in modern software engineering practices, including version control, testing, and CI/CD.
• Experience with formal property verification, assertion-based verification (SVA), or static timing/lint tools.
• A track record of learning across disparate domains (AI/ML and hardware design) and combining them into novel engineering solutions.

Salary range is $160,500 to $200,000 depending on experience, level, and business need. This role may be eligible for discretionary bonus, incentives and benefits.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

Voluntary Self-Identification

For government reporting purposes, we ask candidates to respond to the below self-identification survey.Completion of the form is entirely voluntary. Whatever your decision, it will not be considered in the hiringprocess or thereafter. Any information that you do provide will be recorded and maintained in aconfidential file.

As set forth in Astera Labs’s Equal Employment Opportunity policy,we do not discriminate on the basis of any protected group status under any applicable law.

If you believe you belong to any of the categories of protected veterans listed below, please indicate by making the appropriate selection.As a government contractor subject to the Vietnam Era Veterans Readjustment Assistance Act (VEVRAA), we request this information in order to measurethe effectiveness of the outreach and positive recruitment efforts we undertake pursuant to VEVRAA. Classification of protected categoriesis as follows:

A "disabled veteran" is one of the following: a veteran of the U.S. military, ground, naval or air service who is entitled to compensation (or who but for the receipt of military retired pay would be entitled to compensation) under laws administered by the Secretary of Veterans Affairs; or a person who was discharged or released from active duty because of a service-connected disability.

A "recently separated veteran" means any veteran during the three-year period beginning on the date of such veteran's discharge or release from active duty in the U.S. military, ground, naval, or air service.

An "active duty wartime or campaign badge veteran" means a veteran who served on active duty in the U.S. military, ground, naval or air service during a war, or in a campaign or expedition for which a campaign badge has been authorized under the laws administered by the Department of Defense.

An "Armed forces service medal veteran" means a veteran who, while serving on active duty in the U.S. military, ground, naval or air service, participated in a United States military operation for which an Armed Forces service medal was awarded pursuant to Executive Order 12985.