Senior ASIC RTL Designer (Santa Clara County)

Job Type: Contract

Duration: 6+ Months

Workplace Type: Onsite in San Jose, CA

*******Please Note: We do not provide sponsorship

Job Description

Triple Crown is seeking a Senior ASIC RTL Design Engineer to own the microarchitecture and RTL design of complex, high-speed processor blocks. This role involves building IP from the ground up and taking blocks from initial specification through integration and working silicon.

Responsibilities

• Define microarchitecture and develop synthesizable Verilog/SystemVerilog RTL for complex processor blocks.
• Own ground-up IP and block design from specification through RTL implementation, integration, and silicon bring-up.
• Design data paths, control logic, custom logic, and protocol interfaces with a focus on performance, power, and area (PPA).
• Define block interfaces, document design decisions, and evaluate microarchitectural trade-offs.
• Partner with architecture, verification, physical design, and firmware teams to meet functional, timing, power, and area targets.
• Support block-level synthesis, timing closure, and DFT readiness.

Requirements

• Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of ASIC design experience, including substantial block-level RTL design and silicon development.
• Demonstrated experience taking ground-up IP or complex blocks from microarchitecture and RTL through working silicon.
• Expert-level Verilog/SystemVerilog skills and hands-on experience with synthesis, timing closure, and DFT concepts.
• Strong high-speed design experience, ideally with core processor design.
• Deep understanding of data-path and control logic design and PPA optimization.

Preferred

• Experience designing machine learning accelerators, AI chips, or related hardware.
• Experience using machine learning tools in chip design workflows.

Benefits:

• Paid weekly!
• Health, Dental and Vision Insurance
• 401k