Senior RTL Design Engineer - Low-Power SoC & Equity

Efficient Computer in San Francisco, CA is seeking a Senior Design Engineer to design, integrate, and sign off RTL for blocks across the power-efficient SoC, including on-chip interconnects and memory interfaces. You will take blocks from microarchitecture specs through synthesis-ready RTL and help tape out industry-leading ultra-low-power solutions. This is a hands-on role joining a growing HW engineering team as we move from initial product development to market release and scaled volume