UVM Digital Verification Engineer (FPGA/ASIC)
$75k - $156kDraper
Draper, a nonprofit R&D company in Cambridge, is seeking a UVM Digital Verification Engineer. You will tackle verification challenges in FPGAs and ASICs, applying modern strategies to complex designs in security, cryptography, and more. The role demands a bachelor’s in Engineering and 3-5 years of experience. Benefits include work-life balance programs and competitive salary ranging from $75,000 to $156,000. #J-18808-Ljbffr Draper
Vacancy posted 2 days ago
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