Design & Validation Intern - Engineering

Tenstorrent is leading the industry on cutting‑edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC‑V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. At Tenstorrent, we believe the future of computing must be open, which is why our interns don’t just watch from the sidelines - they help build the core of it. We provide a "code-to-career" pipeline where students collaborate with industry experts to solve high‑stakes problems in RISC‑V and AI hardware‑software co‑design. By joining us, you are taking an internship to democratize high‑performance computers that are accessible to everyone.
As a Design Verification Engineer Intern on the SoC Digital Verification team, you will help ensure the functional correctness and robustness of Tenstorrent’s next‑generation RISC‑V and AI accelerator SoCs. You will work on building and improving modern verification environments, developing tests and checkers, and analyzing coverage to sign off complex digital IP and subsystems. Your work directly contributes to the reliability of the chips that power our AI and high‑performance computing roadmap.
This role is hybrid, based in our Boston, MA office.
S or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field with a focus on digital design and verification .
Strong understanding of digital logic design and computer architecture (pipelines, caches, interconnects, memory systems).
Comfortable working in Linux‑based development environments and using scripting languages (e.g., Python, Shell, Perl ) to automate tasks.
Collaborative team member with clear communication skills, able to document work and discuss trade‑offs with RTL, architecture, and validation teams.
What We Need Help develop and maintain SystemVerilog/UVM testbenches for SoC IP blocks and subsystems, including stimulus, checkers, and scoreboards.
Partner with cross‑functional teams (architecture, design, performance, validation) to align on expected behavior and sign‑off criteria for silicon.
Have impact measured through coverage metrics achieved, quality and reproducibility of bugs found, and robustness of the verification environment you help build.
What You Will Learn Industry‑standard verification methodologies (SystemVerilog/UVM) , including testbench architecture, stimulus generation, and scoreboard/checker design.
Hands‑on experience with simulation, regression, and coverage tools used in large‑scale industrial verification environments.
How to read and interpret hardware specifications , micro‑architecture documents, and timing diagrams, and translate them into actionable tests and assertions.
Exposure to high‑performance interconnects, memory controllers, and accelerators , and how they are verified at IP, subsystem, and SoC levels.
Best practices for collaborating in a silicon development team , including code review, documentation, and cross‑site communication.
USA Hiring Timelines This internship opportunity is available throughout our 3 terms with the following corresponding recruitment cycles:
Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.As set forth in Tenstorrent University Jobs’s Equal Employment Opportunity policy, we do not discriminate on the basis of any protected group status under any applicable law.
If you believe you belong to any of the categories of protected veterans listed below, please indicate by making the appropriate selection. As a government contractor subject to the Vietnam Era Veterans Readjustment Assistance Act (VEVRAA), we request this information in order to measure the effectiveness of the outreach and positive recruitment efforts we undertake pursuant to VEVRAA. A "disabled veteran" is one of the following: a veteran of the U.S. military, ground, naval or air service who is entitled to compensation (or who but for the receipt of military retired pay would be entitled to compensation) under laws administered by the Secretary of Veterans Affairs; or a person who was discharged or released from active duty because of a service‑connected disability.
A "recently separated veteran" means any veteran during the three-year period beginning on the date of such veteran's discharge or release from active duty in the U.An "active duty wartime or campaign badge veteran" means a veteran who served on active duty in the U.An "Armed forces service medal veteran" means a veteran who, while serving on active duty in the U.S. military, ground, naval or air service, participated in a United States military operation for which an Armed Forces service medal was awarded pursuant to Executive Order 12985.

#