Wireless Design Engineer

Role Number: 200661703-3956

Summary

Come join Apple’s growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development with a particular emphasis on highly energy efficient design and new technologies that transform the user experience at the product level. All of which is driven by a world-class vertically integrated engineering team, spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation and FW/SW engineering.

Description

In this highly visible role, you will be at the center of a silicon design group, with a critical impact on getting innovative and functional products to hundreds of millions of customers quickly. As a Wireless Design Engineer, you will be responsible for RTL design of wireless MAC and its interface with the rest of the wireless SoC. You will interact with the software team, wireless system team, and design verification team to develop the best-in-class wireless MAC IPs that ensure the most advanced features and performance, with optimal power and area trade-off.

Minimum Qualifications

• BS and a minimum of 10 years relevant industry experience

• Proven track record of high performance designs in high volume production for low power applications

• Solid background in computer architecture including one or more of the following: Bus fabric, especially APB/AHB/AXI, Memory systems, System debug architecture, Power management with multiple power domains, Encryption/decryption engines, Integer and floating-point numeric units, High-speed data path and control units.

• Experience in ASIC design front end flows – Lint, CDC, STA, LEC

• Knowledge and experience in MAC layer of wired/wireless communication system preferred

• Knowledge of wireless protocols such as Bluetooth, WLAN, or Zigbee preferred

Preferred Qualifications

• 5+ years of hands-on experience in ASIC design flow

• SoC top-level integration experience and system architecture knowledge is a plus

• Proficiency in HDL languages, such as Verilog / SystemVerilog

• Scripting languages (Shell, Perl, Python) desirable

• Ability to work well in a team and be productive under aggressive schedule

• Excellent communication skills and self-motivation/organization