SOC Design Verification Engineer

Job Description

Job Description

We are seeking an experienced SoC Design Verification Engineer with a strong background in UVM-based verification and SystemVerilog to join our dynamic engineering team. The ideal candidate will have hands-on experience in developing and executing complex verification environments, integrating C/C++ models, and debugging issues at both IP and subsystem levels.

Key Responsibilities:

• Develop, implement, and maintain UVM-based verification environments for SoC and IP-level designs.

• Write and execute SystemVerilog assertions to validate design functionality and performance.

• Integrate C/C++ reference models within verification testbenches and ensure seamless co-simulation.

• Perform debugging at IP and subsystem levels , identifying and resolving functional and timing issues.

• Collaborate with design, architecture, and validation teams to define verification plans, strategies, and coverage goals.

• Review and analyze waveforms, simulation logs, and coverage reports to ensure thorough verification closure.

• Participate in regression management, bug tracking, and documentation for design verification deliverables.

Required Qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field .

• 10+ years of hands-on experience in SoC or IP-level design verification .

• Strong proficiency in SystemVerilog , UVM methodology , and assertion-based verification (ABV) .

• Experience integrating C/C++ models in verification environments.

• Proven debugging skills at both IP and subsystem levels using industry-standard EDA tools (e.g., Synopsys VCS, Cadence Xcelium, or Mentor Questa).

Good to Have:

• Gate-Level Simulation (GLS) and post-silicon verification exposure.

• Experience with Low Power Verification (UPF / CPF) methodologies.

• Familiarity with ARM-based SoC architectures and interconnect verification.

California Pay Range

$160,000—$180,000 USD