Sr Design Verification Engineer - RISC-V & CPU
ManpowerGroup Global, Inc.
Design Verification Engineer - Senior Level (15+years) Duration: 10-12+ Months Contract Locations: Remote (California, Oregon, Washington) Pay Range: $80-$85/hr on W2, 40 Hrs Description The top 6 are must skills and rest are preferred skills, and of course it goes without saying that basic DV skills such as System Verilog/UVM, assertions, coverage, random constraints, etc. Qualifications RISC-V architecture knowledge and verification experience VC Formal DPV App (Datapath Verification) that checks the RTL against
C/C++
models for arithmetic conformance L3 cache coherent system with AXI and CHI interfaces C/C++ Synopsys tools, VCS, VC Formal Python based simulation flow Wide Vector Unit and a Matmul Unit Formal verification SOC System integration required, such as booting Linux OS GLS (Gate Level Simulation) Low Power experience (CPF/UPF) #J-18808-Ljbffr ManpowerGroup Global, Inc.Vacancy posted 2 days ago
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