Senior ASIC Verification Architect: Lead Tape-out Strategy
AnySilicon
Ayar Labs is seeking a Principal Design Verification Engineer to lead verification strategy for its next-generation silicon photonic chip. You will architect scalable UVM environments, set standards, and drive high-quality tape-out while mentoring a team of engineers. Responsibilities include defining verification plans with Architects, debugging RTL/firmware issues, and building regression automation to close coverage. Collaboration with cross-functional teams is essential for success. #J-18808-Ljbffr
Vacancy posted 1 day ago
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