Senior ASIC Design Engineer - Static Timing & STA
Cisco Systems
Cisco Systems, Inc. seeks an ASIC Design Engineer to join the Silicon One team in San Jose, California. This role involves developing methodologies for static timing analysis and collaborating with the Physical Design team to ensure design accuracy. Ideal candidates will hold at least a Bachelor’s degree in Electrical or Computer Engineering and have substantial ASIC Design experience. The position offers a unique opportunity to work within a dynamic team that blends large organization support with a startup culture. #J-18808-Ljbffr Cisco Systems, Inc.
$178.9k - $259k
...Details: Job Description: We are seeking an experienced Senior Static Timing Analysis (STA) Developer to architect, design, and optimize next-generation timing analysis engines for advanced ASIC and FPGA design flows. This role is ideal for someone who has deep...SeniorLocal areaShift work- ...provides a unique experience for ASIC engineers by combining the resources... ..., you'll work on closing timing at block, sub-chip, and... .... Your Impact As an ASIC Design Engineer on the STA team, you will play a... ...pivotal role in extraction and static timing analysis (STA) flow...Suggested
- A leading semiconductor company is seeking an ASIC Design STA engineer in San Jose, California. This role involves building and verifying timing constraints for large SoCs, requiring expertise in SDC development and EDA tools, particularly Synopsys Design Compiler and...Senior
$181.1k - $318.4k
...technology company in California is seeking a senior engineer for their wireless silicon development team. The role involves generating static timing constraints and utilizing scripting skills, with a focus on ASIC design. Candidates must have a BS degree and at least...Senior- ...Together, we advance your career. THE ROLE AMD is looking for an ASIC Design STA engineer to contribute to the development of large SoCs, featuring... ...Your responsibilities will include building and verifying timing constraints for intricate SoC designs. This role demands a...Suggested
$170k - $230k
...life on Mars. SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)... ...generation, place and route, timing, noise, physical... ...signoff closure issues in static timing analysis (STA), noise, logic equivalency... ...Physical Design Engineer/Senior: $170,000.00 - $230,000....SeniorPermanent employmentFull timeTemporary workWorldwideWeekend work- AMD is seeking a Senior ASIC Design Engineer to join their Silicon Design team in San Jose, California. You will be responsible for the complete... ...design lifecycle of cutting-edge embedded products, ensuring timing closure and managing complex IP design. The ideal...Senior
$120k - $192k
Broadcom Inc. is seeking a dedicated ASIC Implementation Engineer to join their team in San Jose, California. This role involves responsibilities such as Physical Design, Verification, and Timing Closure. Candidates must have a Bachelor’s degree in Electrical or Electronics...Senior$136k - $212.75k
...clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible... .... The team collaborates with the front design team to understand the clocking requirements... ..., Power Optimization and Ease of timing closure to innovate and implement new Clocking...SeniorWork experience placement$150k - $220k
...will fundamentally change the design, economics, manufacturing... ...of life. We are seeking a Senior ASIC Design Engineer to join our processor... ...crossings. Support synthesis and timing closure for the processor... ...Familiarity with synthesis flows and static timing analysis in the...SeniorFull timeWork at officeVisa sponsorship$136k - $218.5k
We are now looking for an ASIC Design Engineer. NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world’s leading... ...implement in RTL, and deliver a fully verified, synthesis/ timing clean design. Support post‑silicon validation activities....Senior- ...ROLE: Join AMD's Silicon Design team to design and develop... ...embedded products. As a Senior ASIC Design Engineer, you will own the complete... ...in Verilog RTL coding, timing closure, and physical design... ...(SDC), perform static timing analysis (STA) using industry-standard...Senior
$136k - $218.5k
Senior ASIC Design Engineer page is loaded## Senior ASIC Design Engineerlocations: US, CA, Santa Claratime type: Full timeposted on: Posted Todayjob... ...RTL design and synthesis.* Performing logic and timing verification using advanced CAD tools and semiconductor process...SeniorRemote work$153.5k - $310.5k
## Sr. ASIC Physical Design EngineerApplylocations: San Jose, California, United States of Americatime... ...:**As a block-level Physical Design Engineer, you will contribute to all phases of... ....* generating block/chip-level static timing constraints.* Arrange, analyze, and optimize...SeniorWork experience placementWork at office2 days per week$180k - $210k
...per year Credo is engineering the future of high-speed... ...Cables(AECs) all designed for maximum performance... ...Role As a Principal ASIC Design Engineer, you will... ...with PD, DFT, STA, and integration teams... ...Knowledge of synthesis and static timing analysis. ~ Experience...- A leading semiconductor company is seeking a Senior ASIC Design Engineer to join their Silicon Design team in San Jose, CA. The ideal candidate... ...generation embedded products, ensuring design quality and timing closure. With expertise in Verilog RTL coding and ASIC development...Senior
- A leading technology company is seeking a Cellular ASIC Design Engineer to develop and optimize the design and methodology for integrated circuits... ...a strong VLSI background, with responsibilities including timing closure, power optimization, and collaboration with cross-...Senior
$147.4k - $272.1k
SoC Physical Design Engineer, STA/Timing Join us to help deliver the next groundbreaking Apple product. In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC using...Relocation package- ...leading semiconductor company in California is seeking a Senior ASIC Design Engineer to join their Silicon Design team. In this role, you will... ...candidate will have proven expertise in Verilog RTL coding, timing closure, and the complete ASIC design flow. The position offers...Senior
- ...work in the United States on a full-time, permanent basis. StaffRight... ...recruiting to identify a high-caliber ASIC Physical Design Engineer to spearhead the structural... ...procedures, including RC extraction, static timing analysis (STA), and IR-drop mitigation. Engineer...Permanent employmentFull time
- ...Devices, Inc. is seeking a Sr. Silicon Design Engineer in San Jose, California. This role involves... ...and functionalities verification for ASIC and FPGA development. Applicants must possess... ...languages. This position is full-time and does not require travel. #J-18808-Ljbffr...SeniorFull time
$120k - $220k
...system that will fundamentally change the design, economics, manufacturing and service... ...quality of life. We are seeking a Senior STA Methodology Engineer to join our ASIC design team. In this role, you will own cross-functional timing methodology efforts across multiple...SeniorFull timeWork at officeImmediate startVisa sponsorshipNight shift$200k - $220k
Staff / Senior Staff Physical Design Engineer Bolt Graphics is a semiconductor... ...critical role in achieving timing, power, and area (... ...using advanced STA methodologies (OCV/POCV... ...of experiencein ASIC physical design Proven... ...verification Static Timing Analysis (STA...Senior- A leading semiconductor company seeks a Technical Staff Engineer-Design to provide technical leadership for their Enterprise Flash Controller product line, focusing on ASIC/SoC design. The ideal candidate should have over 12 years of experience, strong knowledge in PCIe...Senior
- Advanced Micro Devices is seeking a Senior ASIC Design Engineer in San Jose, CA. In this role, you will be responsible for designing and developing innovative IPs for next-generation embedded products. You will oversee the complete RTL design lifecycle, ensuring high-quality...Senior
- Advanced Micro Devices in Santa Clara is looking for a skilled engineer to contribute to ASIC design for high-performance network chips. You'll work within the NTSG ASIC Design Team focusing on achieving first-pass silicon success through collaboration with architecture...Senior
$136k - $264.5k
NVIDIA Corporation is seeking a Senior Physical Design Engineer located in Santa Clara, California. The successful candidate will drive physical design and timing, partner with mixed signal teams, and perform physical verification checks. Candidates should possess a BS...Senior$180k - $223k
A cutting-edge technology company in San Jose is seeking an ASIC Sr. Staff Engineer responsible for the design and debug of complex digital subsystems. The ideal candidate will have a BS or MS in Electrical Engineering and over 5 years of experience in ASIC design and...Senior- A leading technology company in Santa Clara is seeking an experienced Compiler Circuit Design Engineer to contribute to innovative ASIC design. In this role, you will drive the development of SRAM and register files, collaborate with compiler vendors, and integrate new...Senior
$181.1k - $318.4k
Apple Inc. in Sunnyvale, California is seeking a Wireless Design Engineer to join their wireless silicon development team. This role involves... ...specifications, and ensuring high performance low power ASIC designs. The ideal candidate should have at least a BS degree...Senior
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