US_East | Network Design Engineer_L3

Description:

Possible 3 Month CTH | No Fees | Do Not Re-Post | Confidential
Skype interview is mandatory please provide the candidates skype ID, VIDEO INTERVIEW IS MANDATORY. NO CPT ALLOWED.


Submit candidates under their legal name and use only Capgemini template
Candidate's photo ID IS MANDATORY FOR ALL CANDIDATES EVEN CITIZENS.


In your submission include:
Phone #:
Email address:
Location (City and State):
Relocate:
Availability to start:
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Hiring Status: C2C/W2/1099QOpen for CTH (y/n):
Timeslots for Skype interview (provide Skype ID)
Due to additional onboarding requirements, a meet and greet is required for all new hires.
Candidates must be willing to go to the closest Capgemini, Client, or offsite location as indicated by project team to meet with a Capgemini team member prior to starting their assignment.
If the candidate is not local, travel will be required at the expense of the Capgemini project team (will receive project code for vendor to submit invoices in SAP Fieldglass for reimbursement). If travel is involved, will send travel policy document for the candidate to adhere to


Vendors: If your candidate is selected for interview, you need to take screenshot of candidate and interviewer once interview is initiated. THIS IS NOW MANDATORY FOR ALL INTERVIEWS to confirm candidate is same as person in CV.


Marie Samayoa
OBO Tactical Procurement | Procurement
Capgemini North America | Guatemala
Email: View email address on click.appcast.io


Role: Design Verification Engineer
Work Location: San Francisco, CA - Santa Clara, CA


Design Verification
Minimum Qualifications:
• Proven track record of 'first-pass success' in ASIC development cycles.
• Bachelor's degree in computer science, Computer Engineering, or a related technical field
• 8 to 10 years of hands-on experience with System Verilog/UVM methodology/Assertions/functional coverage
• Experience in ARM Based SoC verification
• Experience with AXI/AHB/APB
• Proficiency with EDA tools and scripting languages (Python or TCL or Perl or Shell)
• Knowledge of C or C++
Responsibilities:
• Work on subsystems with multiple processors (ARM/RISC) and NOC, focusing on integration testing, and top-level functionalities.
• Utilize your experience with UVM-based SoC verification.
• Apply your working knowledge of C to understand existing code, write basic tests, compile, and create hex code for processor tests.
• Engage in design verification involving concurrency and simultaneous memory access.
• Define and implement SoC verification plans and build verification test benches for sub-system/SoC level verification.
• Develop functional tests based on the verification test plan.
• Drive design verification to closure using defined metrics for test plans, functional, and code coverage.
• Debug, root-cause, and resolve functional failures in the design in collaboration with the Design team.
• Collaborate with cross-functional teams (Design, Model, Emulation, and Silicon validation) to ensure the highest design quality.
• Develop and drive continuous improvements in design verification using the latest methodologies, tools, and technologies.
• Utilize your experience with UVM-based SoC verification.
• Apply your working knowledge of C to understand existing code, write basic tests, compile, and create hex code for processor tests.
• Engage in design verification involving concurrency and simultaneous memory access.
• Define and implement SoC verification plans and build verification test benches for sub-system/SoC level verification.
• Develop functional tests based on the verification test plan.
• Drive design verification to closure using defined metrics for test plans, functional, and code coverage.
• Debug, root-cause, and resolve functional failures in the design in collaboration with the Design team.
• Collaborate with cross-functional teams (Design, Model, Emulation, and Silicon validation) to ensure the highest design quality.
• Develop and drive continuous improvements in design verification using the latest methodologies, tools, and technologies.
Named Job Posting? (if Yes - needs to be approved by SCSC)
Additional Details

• Global Grade : C
• Named Job Posting? (if Yes - needs to be approved by SCSC) : No
• Remote work possibility : (No Value)
• Global Role Family : 60239 (P) Cloud Infrastructure
• Global Technical Skills Family : 6246 (T) Network operate & administration Technologies
• Local Role Name : Design Verification Engineer
• Local Skills : Julie Skidmore
• Languages Required: : English