Senior ASIC Design & Verification Engineer - Hybrid Sunnyvale
Salt
Salt in Sunnyvale, CA seeks an experienced ASIC Design and/or Verification Engineer (Sr. to Principal) for a hybrid role. You will architect and verify modules for high-performance networking chips, write detailed specs, and implement RTL using Verilog/SystemVerilog. Collaborate with the physical design team for timing closure, create coverage with SVA, and mentor junior engineers to ensure full block validation and robust netlists. #J-18808-Ljbffr
Vacancy posted 3 days ago
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