Entry-Level ASIC Verification Engineer (UVM/RTL) Equity
NVIDIA Gruppe
NVIDIA Gruppe is seeking an entry-level ASIC Verification Engineer in Austin, Texas. This role involves creating a high-impact system-level IP for performance measurement across multiple projects. The ideal candidate will focus on verification methodologies, ensuring high-quality system-level IP design. Responsibilities include designing verification environments, developing test plans, and collaborating with cross-functional teams. Strong skills in System Verilog, Python, and a relevant degree are required, along with a passion for verification. The position offers a competitive salary and equity benefits. #J-18808-Ljbffr NVIDIA Gruppe
$116k - $189.75k
...SOC) group is looking for an entry level ASIC Verification Engineer! In this position you will... ...the corresponding design (RTL). For this position, you should... ...the design. Create the UVM components, sequences, tests... ...will also be eligible for equity and benefits. Equal Opportunity...Employment EquityEntry level- ...Austin is seeking an experienced ASIC Verification Engineer to work on system-level IP projects. Candidates should have... ...with expertise in System Verilog and UVM. This position offers a... ...experience and location, as well as equity and benefits. Join a team that values...Employment Equity
$116k - $189.75k
NVIDIA is looking for an ASIC Verification Engineer to help verify our... ...and verify generated RTL Ensure code and functional... ...components using SV/UVM methodology Drive coverage... ...at the IP or block level Experience developing... ...also be eligible for equity and benefits. Applications...Employment Equity$136k - $212.75k
...looking for an experienced ASIC Verification Engineer! In this position you... ...to create a high-level and broad impact at NVIDIA... ...corresponding design (RTL). For this position,... ...the design. Create UVM components, sequences,... ...also be eligible for equity and benefits . Applications...Employment Equity- ...TX is seeking a Senior Design Verification Engineer to lead verification efforts for ASICs in 5G infrastructure. The... ...involves building transaction-level models, designing UVM testbenches, and driving hardware... ...should have extensive RTL verification experience and strong...Suggested
- A leading semiconductor company in Texas is seeking a Design Verification Engineer to join its team. This role involves planning and executing the... ...using advanced techniques and tools like System Verilog and UVM. The ideal candidate will have a strong background in...
- An established industry player is seeking a skilled Hardware Verification Engineer to join their dynamic team in Austin. In this pivotal role,... ...for technology and a strong background in hardware verification, this opportunity is perfect for you. #J-18808-Ljbffr Core Asic
$84k - $156k
## Digital Verification Engineer IApplylocations: Austintime type:... ...reliability of Silicon Labs’ ASIC IP used in IoT... ...plus:** Knowledge of UVM (Universal Verification... ...related to verification, RTL development, or... ...and Roth plan option* Equity rewards (RSUs)* Life/AD...Employment EquityInternshipFlexible hours- ...MSIP organization) is looking for an ASIC Design Verification Engineer to join our growing team. We develop leading... ...and directed) using System Verilog/UVM/SystemC Triaging and debugging... ...knowledge and ability to debug System Verilog RTL code using simulation tools...
- ASIC Design Verification Engineer - Austin, Texas Hybrid work schedule. This is not a remote... ...Build transaction‑level models (TLM) that drive early... ...to chip. Design and build UVM testbenches from scratch, not... ...years of hands‑on, industry RTL verification experience in...Temporary work
$158k - $243k
...of exceptional engineers whose mission is... ...Digital IC Verification Engineer will be... ...experience in digital ASIC verification... ..., RTL, verification and... ...low power gate level simulations Exposure... ...methodologies such as UVM Knowledge of... ...components: salary and equity. Guidance on...Employment EquityFull timeTemporary workLocal areaFlexible hours$166k - $249k
...Category Engineering Hire Type Employee Job ID 151... ...lead in chip design, verification, and IP integration, empowering... ...and highly skilled ASIC Digital Verification... ...SystemVerilog and UVM. Collaborating with... ...for an annual bonus, equity, and other discretionary...Employment EquityRemote work$170k - $285k
...Senior / Staff Digital Verification Engineers with a strong... ...through verified RTL, sign-off, and silicon... ...SystemVerilog/UVM, including constrained... ...RTL and gate-level sign-off Support... ...high-performance ASICs or SoCs Ownership... ...platforms Compensation & Equity Competitive Salary...Employment EquityPermanent employmentTemporary workWork at officeLocal areaRelocationVisa sponsorship$136k - $218.5k
...Austin, Texas is seeking an experienced ASIC Design Engineer to join the SOC group. The role... ...delivering methodologies for system-level IP, debugging RTL checks, and working collaboratively... ...range from $136k to $218.5k, along with equity and benefits. #J-18808-Ljbffr NVIDIAEmployment Equity$168k - $264.5k
...Corporation is seeking a Senior ASIC RTL Integration and Netlisting Engineer in Austin, Texas. This role... ..., strong knowledge of verification tools, and proficiency in scripting... ...$168,000 to $264,500 for Level 4 depending on experience, with equity eligibility and a...Employment Equity- ...Austin, Texas, is seeking an ASIC Design Engineer to join the System-On-Chip group... .... You will influence system-level IP and performance across... ...methodologies and delivering RTL for optimal performance. The... ...experience and location, as well as equity and additional benefits. #J-...Employment Equity
- ...company in Austin, Texas, is seeking a Senior / Staff Digital Verification Engineer to oversee the verification processes for high-speed silicon... ...and benefits package includes competitive salary, equity options, and comprehensive health coverage. #J-18808-Ljbffr...Employment Equity
- ...GmbH in Austin, Texas is looking for an ASIC Design Verification Engineer to join their team. This role involves building transaction-level models and performing block-level ASIC verification... ...track record with SystemVerilog and UVM. In addition to a competitive salary,...
$168k - $264.5k
Senior ASIC RTL Integration and Netlisting Engineer page is loaded## Senior ASIC RTL Integration... ..., GPUs, SoCs at block level, cluster level, and/or... ...synthesis and associated verification such as equivalence checking... ...also be eligible for equity and .Applications for...Employment Equity- A leading semiconductor company in Austin is seeking an ASIC Design Verification Engineer to enhance the development of cutting-edge technologies. The... ...abilities, and familiarity with Verilog, System Verilog, and UVM. This role emphasizes teamwork within an innovative...
- ...human life on Mars. SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At... ...verification at block and system level Write and review test... ...methodologies such as UVM/OVM/VMM Strong object-oriented... .... Python for automation RTL design chip bring-up and...Permanent employmentFull timeWorldwideWeekend work
- ...Role: Verification Engineer Location: Austin, TX (Onsite) Duration: 12 months contract JOB DUTIES: • Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort. • Be part of a team of...Contract work
- Senior Design Verification Engineer — ASIC IP Silicon Verification | 5G Infrastructure... ...- building transaction‑level models that give the team early... ...Architecture - designing and building UVM environments from a clean... ...of hands‑on, in‑industry RTL verification experience at...
$220.92k - $311.89k
...innovation in next-generation ASICs for AI applications... .... As a Senior Formal Verification Engineer, you will play a... ...block, subsystem, and SoC levels. Execute verification... ...with architects, RTL developers, and physical... ...techniques. Familiarity with UVM‑based simulation...Local areaShift work- Correct Designs is looking for a Senior Design Verification Engineer with over 8 years of hardware verification experience, particularly in SystemVerilog and UVM methodologies. The role includes verifying complex design blocks, developing test plans, and requires a solid...Remote jobContract work
- Correct Designs in Austin, TX is seeking a talented Design Verification Engineer to ensure the quality of complex design blocks. This role supports... ...experience in verification, proficiency in SystemVerilog and UVM methodologies, and strong analytical skills. The position...Remote jobLong term contract
- Silicon Labs seeks a Digital Verification Engineer I in Austin, Texas, to verify ASIC IP blocks for IoT modem designs. This role requires a degree in Electrical... ...competitive benefits including flexible PTO, 401k matching, and equity rewards. #J-18808-Ljbffr Silicon LabsEmployment EquityFlexible hours
- ...Texas, is seeking a Senior Digital IC Verification Engineer to lead functional verification of neural... ...and at least 3 years of digital ASIC verification experience. Responsibilities... ...Competitive salary is offered alongside equity, medical benefits, and flexible time off...Employment EquityFlexible hours
$100k - $166.75k
As a Formal Verification Engineer at NVIDIA, you will verify the design and implementation... ...best performance. Debug RTL to identify causes of... ...0,000 USD - 166,750 USD for Level 1, and 116,000 USD - 189,750... ...will also be eligible for equity and benefits. Applications for...Employment Equity$191.1k - $258.5k
...skilled and motivated performance analysis engineers to join our diverse team at Arm! Responsibilities Perform RTL performance analysis and verification for SoC Provide technical leadership... ...performance verification plans at SoC-level and performance debug using both...
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