Hardware Engineer

We are looking for highly talented, motivated, and versatile engineers that can create the next generation. As a Hardware Engineer at our company, you will be responsible for architecture, design, and development of next generation Electronic Safe and Arm Devices utilizing the latest state of the art technologies. Responsibilities Analysis of the requirements, architecture definition, design and debug of FPGA and associated hardware and microcontroller products and associated firmware. Developing Verilog HDL targeting Antifuse and enhanced Flash FPGA's. Performing effective analysis of functional issues or performance profiling with the hardware and firmware in test environments or target host systems. Contribute to process improvements to ensure hardware‑firmware quality and time‑to‑market. Qualifications Bachelor's Degree and minimum 6 years of prior relevant experience. Graduate Degree and a minimum of 4 years of prior related experience. In lieu of a degree, minimum of 10 years of prior related experience. Knowledge using Verilog for logic design. Programming experience in C for embedded systems, including development of algorithms, manipulation of data structures, and implementing highly optimized code. Experience with lab tools: logic analyzers, oscilloscopes, JTAG/ICE debuggers, and protocol analyzers. Familiarity with hardware, software, and firmware development methodologies to ensure quality and time‑to‑market (design verification, code reviews, unit testing, prototyping, and product testing). Familiar with code version control repository tools such as Subversion (SVN), GIT or TFS. Digital design practices and principles, logic design and architecture and experience with HDLs (i.e., Verilog, VHDL). Preferred Additional Skills Knowledge using SystemVerilog for verification with AVM, VMM, OVM, or UVM a plus. Developing C# source code targeting enhanced Flash microcontrollers. Good English knowledge (speech and writing). Be action‑oriented and organized. Ability to handle short notice needs/requests. #J-18808-Ljbffr