GPU Logic Design Engineer

Role and Impact As a GPU Logic Design Engineer, you will play a vital role in developing cutting‑edge graphics IPs required for next‑generation GPU designs. By leveraging your expertise in logic design and RTL coding, you will contribute to the creation of functional units, GPU IP blocks, and their integration into system‑on‑chip (SoC) designs. You will collaborate with diverse teams to define architecture and microarchitecture features, optimizing logic to meet power, performance, area, and timing targets. Your work will directly impact Intel's leadership in graphics technology, enabling innovative solutions for a wide range of applications and products. Key Responsibilities Develop RTL code and implement optimized logic designs for GPU IPs, ensuring alignment with architecture and microarchitecture specifications Perform power, performance, area, and timing optimization to meet design goals during physical implementation Participate in defining architecture and microarchitecture features for GPU blocks, contributing to innovation and technology leadership Execute unit‑level verification, debug failing RTL tests, and resolve design issues to achieve correctness, functionality, and robustness at all verification hierarchies Utilize formal equivalence verification (FEV) techniques to ensure design accuracy and fidelity across development stages Collaborate with SoC customers to ensure seamless and high‑quality integration of GPU blocks into full chip designs Drive microarchitecture‑level enhancements and provide technical documentation to support design and development activities Minimum Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 4+ years of experience in RTL design and logic development with expertise in System Verilog Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 3+ years of experience in RTL design and logic development with expertise in System Verilog PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field with 6+ months of experience in RTL design and logic development with expertise in System Verilog Preferred Qualifications Proficiency in low‑power design techniques, including UPF coding and debugging Experience with static timing analysis and formal equivalence verification (FEV) Understanding of GPU architecture fundamentals and digital design principles Technical proficiency in TCL scripting for design automation tasks Demonstrated ability to debug microarchitecture and hardware simulations effectively Advanced knowledge of microarchitecture fundamentals and GPU validation methodologies Experience with power and performance validation and debugging in large‑scale GPU designs Strong communication and collaboration skills, with a track record of working in cross‑functional teams to solve complex problems Job Type Experienced Hire Shift Shift 1 (United States of America) Location Primary Location: US, California, Santa Clara Additional Locations: US, California, Folsom Business Group At the Data Center Group (DCG), we are committed to delivering exceptional products and delighting our customers. We offer broad‑market Xeon‑based solutions and custom x86‑based products, ensuring tailored innovation for diverse needs across general‑purpose compute, web services, HPC, and AI‑accelerated systems. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Annual Salary Range $122,440.00 - $232,190.00 USD (US locations) Work Model This role is eligible for a hybrid work model that allows employees to split their time between working on‑site at their assigned Intel site and off‑site. Job posting details such as work model, location or time type are subject to change. Additional Information Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. #J-18808-Ljbffr Intel