Logic Design Engineer

Responsibilities Involved with the development of DRAM Test Engine, Prefetch Engine, and Memory Controller for DDR4 and LPDDR4 projects using APB/AXI/CHI VIPs, Synopsys VCS, UVM tools, and SystemVerilog, python languages etc. Interact and collaborate with design and micro-architecture teams to review design specifications and understand the functional requirements of the design Apply verification methodologies to verify memory subsystem designs of the computer systems, including the AMBA5 CHI and AMBA4 AXI bus bridges, the DDRx/LPDDRx memory controllers; execute verification tasks to ensure correctness of functionalities in the design Write functional test plans; build UVM-based constrained random test benches, including sequencers, generators, drivers, scoreboard, monitors, checkers, functional coverage and integrate with CHI/AXI verification IPs Write test cases; build Perl/Python scripts to automate the regression tasks; run simulation using Synopsys VCS; debug and report failures in the design; collect functional coverage and code coverage; use coverage tools to analyze and tweak tests for coverage; apply assertion-based verification methodology to facilitate debug; support system integration; build performance test benches on Emulators for silicon bring‑up Requirements Bachelor’s degree in EE, CS or related field, and 2 years of experience in digital logic systems. A Master’s degree in the same disciplines is acceptable in lieu of the two-year experience Design of digital logic systems; Circuit simulation and debugging; RTL simulation and debugging Verification skills such as Verilog debug Standard Electronic Design Automation (EDA) tools: such as cadence virtuoso Scripting: Tcl, Shell, Makefile Linux/UNIX tools, such as grep, awk and vi for creating and editing of EDA tool input files as well as analyzing of EDA tool report files #J-18808-Ljbffr FLC Technology Group