Senior Applications and Solutions Engineer - Foundry Services

Job Details:Job Description: Intel Foundry is a systems foundry transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. Intel Foundry will be differentiated from other foundries by our world class industry-leading IP portfolio that customers can choose from including rich IP ecosystem including x86 cores, graphics, AI, and Arm/RISC-V IPs, world-class design services, and operationally resilient global manufacturing with committed capacity in the US and Europe.Position OverviewWe seek a Senior ASIC Design Engineer to provide technical support to Intel Foundry Services customers on PDKs through ASIC design implementation flows and to perform ASIC physical design execution with specialized focus on complex multi-voltage domain (UPF/CPF) designs and power-intent (VCLP and Conformal LP) verification signoff. This role drives quality improvements in design kits, supports customers through successful tape-outs, and performs ASIC design service on complex multi-voltage domain designs.Key ResponsibilitiesCustomer Technical Support and ASIC Design ExecutionProvide comprehensive technical support to Intel Foundry Services customers on PDKs, digital reference flows and digital design signoff methodologies in multi-voltage domain implementation and verification.Support and deliver ASIC/Digital tool/flow/methodology solutions, especially in multi-voltage domain design implementation and verification using Cadence and Synopsys tool suites. Have deep knowledge of UPF/CPF (level-shifter, isolation, power gating, retention, always-on) implementation and verification using (VCLP and Conformal LP). Have experience in writing and debugging UPF/CPF for multi-voltage domain designs.Drive customer success through expert guidance and have strong hand-on experience in ASIC design executionQuality Assurance and DocumentationDrive quality improvements in design kits and documentation through ASIC design reference flow validation and comprehensive documentation reviewCreate application notes, technical design checklists, and deliver training presentations to customers and internal teamsEstablish and maintain high quality design through implementation and verification methodologies and checklistsCore CompetenciesSelf-driven and results-oriented with ability to manage multiple tasks effectivelyStrong teamwork skills to drive solutions for implementation challengeAnalytical problem-solving capabilities for complex design issuesExcellent communication skills with experience in collaboration and customer feedbackQualifications:The Minimum qualifications are required to be considered for this position. Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum QualificationsUS Citizenship required.Ability to obtain a US Government Security Clearance.Bachelor's degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of study.4+ years of experience with advanced CMOS processes (16nm and below).3+ years of experience in ASIC design implementing and verification in area of low power, multi-voltage domain3+ years of experience in scripting languages like Python, Perl, Tcl, and/or shell scriptingPreferred QualificationsActive US Government Security Clearance with a minimum of Secret levelPost Graduate degree in Electrical / Computer Engineering, Computer Science, or in a STEM related field of studyExperience with state-of-the-art process technology (7nm and below)Hands-on experience in physical design Implementation and verification methodology for multi-voltage domain in SoC designExperience using EDA tools for multi-power domain design (UPF/CPF) implementation and power-intent verification (VCLP, Conformal LP) at block and at SOC levelExperience in writing and debugging UPF/CPF for multi-voltage domain designsCustomer-facing experience in technical support roles# cjJob Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Arizona, PhoenixAdditional Locations:US, California, Santa Clara, US, Oregon, HillsboroBusiness group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.SummaryLocation: US, Arizona, Phoenix; US, California, Santa Clara; US, Oregon, HillsboroType: Full time