Physical Design Engineer, Timing
$100kTenstorrent
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.Tenstorrent is looking for a mid- to senior-level Physical Design Engineer with a strong background in static timing analysis (STA). In this role, you will help converge multi-million-gate designs on advanced process nodes and partner with cross-functional teams through final signoff and tapeout.This role is hybrid, based out of Austin, TX, Fort Collins, CO, or Santa Clara, CA.We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.Who You AreA physical design engineer with 8+ years of experience in STA, timing closure, and advanced-node design implementation.Experienced with timing flows, constraints, clocking, CDC, RDC, derates, uncertainties, guardbanding, and final signoff.Skilled in writing and debugging SDC constraints, creating ECOs, developing closure strategies, and analyzing worst-case corners.A strong collaborator and communicator who can drive results across distributed, cross-functional engineering teams.What We NeedDrive timing convergence across blocks, partitions, sections, and top-level designs; generate and validate timing models and publish results.Analyze timing violations, develop and propagate fixes, debug timing-flow issues, and keep execution progressing through tapeout.Develop and validate bottom-up constraints while partnering with Design and DFT teams on methodology updates and closure requirements.Use Python, Perl, and Tcl for automation and flow development; experience with SPICE, PNR, placement, CTS, routing, post-route optimization, DFT, or AI-based automation is a plus.What You Will LearnHow to develop scalable timing models, constraints, and closure strategies across multiple levels of design hierarchy.How clocking, guardbanding, derates, uncertainties, CDC, RDC, and process corners influence timing convergence.How timing, physical design, Design, and DFT methodologies come together to deliver successful tapeouts.How to improve implementation and signoff workflows through scripting, automation, flow development, and emerging AI-enabled solutions.Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.This position requires access to technology that requires a U.S. export license for persons whose most recent country of citizenship or permanent residence is a U.S. EAR Country Groups D:1, E1, or E2 country. This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
$176.6k - $247.3k
...Acceleration team you’ll be responsible for the design and optimization of Hardware in our... ...for block and full-chip level static timing analysis • Write, debug & validate... ...collaboration and teamwork with other physical design engineers as well as with the RTL/Arch. teams...SuggestedFull timeLocal areaFlexible hours$198.7k - $298.1k
...Technologies, Inc. Job Area: Engineering Group, Engineering Group CPU... ...engineers in the world to create designs that push the envelope on... ...to define, develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer, you will...SuggestedWork experience placementWork from home$198.7k - $298.1k
...Qualcomm Technologies, Inc.## Job Area:Engineering Group, Engineering Group CPU... ...in the world to create designs that push the envelope on performance... ...to define, develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer, you will...SuggestedWork experience placementWork from home- ...GPU Physical Verification Design Engineer Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance... ...Experience with Floorplanning tools, P&R flows, global timing verification and Physical Design Verification Flows is...Suggested
$125.7k - $203.1k
...Because full product development—from design to qualification to production—is within... ...the digital world. Your Impact As a Physical Design Engineer, you will play a key role in the full... ...You will optimize floor planning and timing, analyze and improve backend design flows...SuggestedFull timeTemporary workWork experience placementInternshipLocal areaFlexible hours- Lightmatter is hiring a Physical Design Timing Engineer in Mountain View, California. You will help drive backend digital execution for photonics-based interconnect solutions, working alongside world-class engineers. Ideal candidates have extensive experience in ASIC STA...
$2,000 per month
...frontier intelligence. We co-design chips, racks, software, and manufacturing... ...and staffed by leading engineers, Etched is redefining the... ...inference clusters. As a Physical Design Methodology Engineer,... ...speeds, directly accelerating our time-to-market and enabling PPA...Work at officeRelocation package$184.7k - $324.8k
...opportunity for a forward‑thinking and unusually hardworking Physical Design Engineer. As a member of our wide‑ranging group, you will have the... ...center of a PHY design effort working with architecture, CAD, timing, and logic design teams, with a critical impact on...Relocation$190.2k - $285.4k
Company:Qualcomm Technologies, Inc.Job Area:Engineering Group, Engineering Group ASICS... ...future for all.Qualcomm is seeking talented Physical Design Engineers to join our growing SoC and... ...Tree Synthesis, low power implementation, timing analysis, design methodology,...Work experience placementWork from home- ...adhering to strict schedules and design goals. Work closely with... ..., RTL designers, and DFT engineers to resolve implementation and... ...Help close EM/IR, drive LEC and physical verification signoff for your... ...encompassing synthesis, PnR, timing convergence and physical...Temporary workWork at office
- ...Technologies group, you’ll help design and manufacture our next-... ...requires a mix of strategic engineering along with hands‑on, technical... ...have hands on experience in physical design and large chip integration... ...tools, P&R flows, and global timing verification Flows is...
- ...intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer, Netlisting to join our dynamic and growing team. What... ...etc. Help in all aspects of physical design, such as driving timing convergence, timing constraints generation and management,...Shift work
- ...interconnects to scalable photonic engines, Lumilens is unlocking a new... .... Every line of code, every design decision, every breakthrough... ...We are seeking a Senior Physical Design Engineer to join our... ...implementation from RTL to GDSII, drive timing and power closure for ultra‑...
$168k - $264.5k
...We are now looking for a motivated Physical Design Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part... .... What you'll be doing: Drive physical design and timing from netlist to gds. Partner with mixed signal teams to...- ...performance, multi-gigabit SerDes PHY and advanced IP designs. In this Physical Design Engineering role, you will contribute across the full RTL-to-GDS implementation... ...lifecycle, working on challenging designs where timing, power, area, and physical quality are critical....
- ...Job Title: Physical Design Engineer Location: Santa Clara, CA THE ROLE: This is a Physical Design Engineering role that will require... ...the design from RTL to GDS with synthesis, Place n Route, timing, and Physical Verification. RESPONSIBILTIES: This engineer...Work experience placement
- ...Ampere is a semiconductor design company for a new era, leading... ...About The Role As part of the Physical Design team at Ampere, you... ...Floorplan, Place and Route, Timing closure, LEC, IR/EM and DRC/LVS... .... Being a Physical Design Engineer at Ampere is interesting, challenging...Local areaWorldwide
- ...Physical Design Engineer Required Skills & Experience- Bachelors with 5-8 years of experience, or Masters with 3-8 years of experience... ...Experience with Floor Planning and Layout, Place and Route, and Timing Closure Bachelor's degree required (preferably Electrical...Work experience placementRelocation packageFlexible hours
$180k - $280k
...builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows... ...The Role Join our close-knit physical design team where you will drive high-impact PPA... ...tools. ~ BS or MS in Electrical Engineering. Preferred: ~ Knowledge of high...Full time- ...Physical Design Engineer We're looking for a hands-on Physical Design Engineer to support complex SoC projects for our client who designs and... ...: Pre-layout STA for feasibility and timing constraint validation Chip/block-level floor planning and...Local area
- ...Physical Design Engineer Building AI chips that are hard-coded for individual model architectures. Seeking exceptional PD engineers to join... ...to GDSII sign-off ~ Experience with back-end design and timing closure on 3nm-7nm ~ Experience with UPF-based low power...
$2,000 per month
...would be impossible with GPUs, like real-time video generation models and extremely... ...-tier investors and staffed by leading engineers, Etched is redefining the infrastructure... ...Etched is looking for exceptional Physical Design engineers to join our team. In this role...Work at officeRelocation package$160k - $220k
...computing. About the Role Join our Physical Design (SoC Integration) team responsible for... ...to GDS. As a Sr. Staff Physical Design Engineer, you will lead physical implementation... ...Compiler or Cadence Innovus) Drive timing closure and signoff using PrimeTime (PT...- ...Physical Design Engineer - Location: San Jose OR Irvine, CA Our client develops specialized semiconductor solutions for the edge, building processors... ..., floor planning, power grid creation, place and route, timing analysis, noise analysis, physical verification, EM/IR...Full timeH1bVisa sponsorshipRelocation package
- ...Position - 5 Days Onsite Skill Required: Physical Designing with Innovus tool experience What... ...Synthesis, Physical Verification, and Timing Closure Setup and Synthesizing RTL... ...Collaborating with IC Design RTL Engineers What you will Bring: TCL/PERL...Full time
$129.4k - $207k
...Please Note: 1. If you are a first time user, please create your candidate login account before you apply for a job. (... ...apply. Job Description: Broadcom is searching for a Physical IC Design Engineer to join the Data Center Solutions Group at our main campus...Full timeLocal areaRemote work$100k
...of all seniorities. Tenstorrent is seeking a talented Physical Design Engineer to implement high-performance blocks for our industry-leading... ...EE/ECE/CE/CS with proven experience in synthesis, PnR, and timing closure on taped-out designs. Expertise with industry-...Permanent employment$150k - $170k
...eInfochips (An Arrow Company) Semiconductor and Engineering Talent Acquisition Professional !!! Position: Sr. Physical Design Engineer (eInfochips Inc) Experience: 10+... ...closure at both block and top levels, addressing timing, congestion, IR-drop, and physical verification...Full timeTemporary workWork at office- ...future. Whether you’re designing next-gen processors, enabling... ...contribute to advanced-node physical design for complex ASIC and SoC... ...products, driving implementation, timing closure, signoff, and design... ...CAD, technology, and product engineering teams, you will help deliver...
$170k - $230k
...Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA SpaceX was founded under the belief that a future where humanity... ...floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage...Permanent employmentTemporary workWorldwideWeekend work
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