Sign up to access all features of our service.
  • Job search
  • Favorites
  • Create a CV
    New
  • Salaries
  • Subscriptions

ASIC Physical Design Engineer II (Full Time) - United States

$125.7k - $203.1k

CISCO Systems

Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens.Applications accepted until further notice.Meet the Team The Silicon One team creates innovative hardware platforms central to the AI era, powering Cisco’s core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we’re able to think differently, experiment more, and work quickly. Join us to power the future of the digital world. Your Impact As a Physical Design Engineer, you will play a key role in the full RTL-to-GDSII implementation flow for advanced semiconductor nodes. You will optimize floor planning and timing, analyze and improve backend design flows, and collaborate across teams to ensure the successful delivery of high-performance networking chips. You will: Own and drive RTL-to-GDSII implementation for advanced nodes (sub-16nm to 3nm). Define and execute hierarchical floor planning, place and route, clock and power distribution, and timing convergence strategies. Perform static timing analysis (STA), setup reviews, and sign-offs for multi-mode/multi-corner designs; develop automated scripts within STA tools. Implement and manage timing ECO strategies using tools like Tweaker/PrimeTime. Analyze quality and efficiency gaps, recommend tool, flow, and methodology improvements. Collaborate with RTL, DFT, EDA vendors, and tool owners to drive design and implementation efficiency. Evaluate and implement new timing methodologies; provide creative debugging solutions. Contribute to best practices and drive methodology alignment across projects. Minimum Qualifications Meet one of the following (completed within the past 3 years or expected to be completed within the next 12 months):  -A Master's degree with 0 years of work experience; or  -A Bachelor's degree with 2 years of work experience.  Qualifying education and work experience should be in ASIC Physical Design, ASIC design, engineeringor a related field.  Foundational knowledge of ASIC physical design and implementation flows gained through academic projects, internships, or relevant coursework. Understanding of physical design concepts, including floor planning, clock tree synthesis, power distribution, and I/O planning. Exposure to the physical design lifecycle, including logic synthesis, placement, routing, and basic timing closure. Preferred Qualifications Proficiency in scripting languages such as Python, Tcl, or Perl for task automation and data analysis. Hands-on experience with industry-standard EDA tools (e.g., Cadence Innovus, Synopsys ICC2, or Synopsys Design Compiler) through lab work or internships. Familiarity with physical verification processes (DRC/LVS) using tools such as Mentor Calibre or Synopsys ICV. Exposure to static timing analysis concepts and tools, such as PrimeTime. Why Cisco? At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere. We are Cisco, and our power starts with you. Message to applicants applying to work in the U.S. and/or Canada:Individual pay is determined by the candidate's hiring location, market conditions, job-related skillset, experience, qualifications, education, certifications, and/or training. The full salary range for certain locations is listed below. For locations not listed below, the recruiter can share more details about compensation for the role in your location during the hiring process.U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance. Please see the Cisco careers site to discover more benefits and perks. Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.U.S. employees are eligible for paid time away as described below, subject to Cisco’s policies:10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by CiscoNon-exempt employees** receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employeesExempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the nextAdditional paid time away may be requested to deal with critical or emergency issues for family membersOptional 10 paid days per full calendar year to volunteerFor non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.Employees on sales plans earn performance-based incentive pay on top of their base salary, which is split between quota and non-quota components, subject to the applicable Cisco plan. For quota-based incentive pay, Cisco typically pays as follows:.75% of incentive target for each 1% of revenue attainment up to 50% of quota;1.5% of incentive target for each 1% of attainment between 50% and 75%;1% of incentive target for each 1% of attainment between 75% and 100%; andOnce performance exceeds 100% attainment, incentive rates are at or above 1% for each 1% of attainment with no cap on incentive compensation.For non-quota-based sales performance elements such as strategic sales objectives, Cisco may pay 0% up to 125% of target. Cisco sales plans do not have a minimum threshold of performance for sales incentive compensation to be paid.The applicable full salary ranges for this position, by specific state, are listed below:New York City Metro Area:$125,700.00 - $203,100.00Non-Metro New York state & Washington state: $111,700.00 - $180,800.00* For quota-based sales roles on Cisco’s sales plan, the ranges provided in this posting include base pay and sales target incentive compensation combined.** Employees in Illinois, whether exempt or non-exempt, will participate in a unique time off program to meet local requirements.Job SummaryJob number: 2024671Profession: Product and Engineering

Vacancy posted 14 hours ago
Similar jobs that could be interesting for youBased on the ASIC Physical Design Engineer II (Full Time) - United States in San Jose, CA vacancy
  •  ...ASIC Physical Design Engineer II [Full Time] – United States Cisco's Silicon One team is seeking a Physical Design Engineer to contribute to the development of innovative hardware platforms that power core Switching, Routing, and Wireless products globally. This role... 
    Full time
    Work experience placement
    Internship

    Anysilicon

    San Jose, CA
    1 day ago
  • $190.2k - $285.4k

    ## Physical Design EngineerSanta Clara, California, United States of AmericaApply NowFind out how well you match with...  ..., Inc.## **Job Area:**Engineering Group, Engineering Group ASICS Engineering**General Summary...  ...low power implementation, timing analysis, design methodology... 
    Suggested
    Work experience placement
    Work from home

    QUALCOMM, Inc.

    Santa Clara, CA
    1 day ago
  • $250.6k - $362.6k

     ...grow. Because full product development—from design to qualification...  ...with physical design teams to...  ...automation targets: timing triage, Congestion...  ...’s degree in Engineering and 15+ years of ASIC related...  ...restricted stock units, which vest following...  ..., by specific state, are listed... 
    Full time
    Temporary work
    Local area
    Flexible hours

    CISCO Systems

    San Jose, CA
    4 days ago
  • Position:Physical Design Engineer II (eInfochips Inc)Job Description:What You'll Be...  ...for assigned partitions of ASIC chip adhering to strict schedules...  ...synthesis, PnR, timing convergence and physical verification...  ...California (eInfochips)Time Type:Full timeJob Category:Engineering... 
    Full time
    Work at office

    Arrow ECS

    San Jose, CA
    4 days ago
  • $136k - $218.5k

     ...Coherent Interconnects Design Team, you will be...  ...for the physical design of CPU on-chip...  ...implementation, synthesis and timing closure while...  ...in Electrical Engineering, Computer Engineering...  ...understanding of ASIC design flow...  ...Santa Clara; US, OR, HillsboroType: Full time
    Full time

    Nvidia

    Santa Clara, CA
    1 day ago
  • $164.47k - $232.19k

     ...every single day to design and manufacture...  ...Impact:As a GPU Physical Design Engineer, you will play a...  ...place and route, timing analysis, and verification...  ....Experience with ASIC design flows such...  ...:Shift 1 (United States of America)...  ...Clara; US, Oregon, HillsboroType: Full time
    Full time
    Internship
    Local area
    Immediate start
    Worldwide
    Shift work

    Intel

    Santa Clara, CA
    2 days ago
  • $136k - $218.5k

     ...are now looking for a motivated Senior ASIC Physical Design Engineer, Netlisting to join our dynamic and...  ...at block level, cluster level, and/or full chip level, with a focus on netlist-related...  ...of physical design, such as driving timing convergence, timing constraints... 
    Full time
    Shift work

    Nvidia

    Santa Clara, CA
    23 hours ago
  • $176.6k - $247.3k

     ...responsible for the design and...  ...for block and full-chip level static timing analysis• Write...  ...teamwork with other physical design engineers as well as with...  ...Understanding of ASIC Physical Design...  ...follow all federal, state, and local laws...  ...stock units (RSUs). Final compensation... 
    Full time
    Local area
    Flexible hours

    Amazon

    Cupertino, CA
    4 days ago
  • $160k - $275k

     ...efficiently as allowed by physics, bringing the...  ...silicon physical design engineers to join our team...  ...equivalency, extraction, timing, power estimation,...  ...experience in ASIC Physical...  ...base salary for this full-time position is determined...  ...under federal, state or local laws,... 
    Full time
    Daily paid
    Work experience placement
    Work at office
    Local area
    Remote work
    Monday to Friday
    Flexible hours

    MatX

    Mountain View, CA
    2 days ago
  • $125.7k - $203.1k

     ...other grow. Because full product development—from design to qualification...  ...Impact As an ASIC Engineer, you will play a...  ...across the physical and digital worlds...  ...restricted stock units, which vest following...  ...periods of time.U.S. employees are...  ..., by specific state, are listed below... 
    Full time
    Temporary work
    Work experience placement
    Local area
    Flexible hours

    CISCO Systems

    San Jose, CA
    4 days ago
  • $186k - $407k

     ...ever.Principal ASIC Design EngineerAbout the...  ...ASIC Design Engineer, you will be the...  ...senior team — united around the goal...  ...blocks, defining timing constraints,...  ...interfaces, and control state machines — in...  ...and modes.Physical Design InterfaceServe...  ...with full front-to-back implementation... 
    Full time
    For contractors
    Local area
    Immediate start

    Micron

    San Jose, CA
    2 days ago
  • $129.2k - $209k

     ...Alto Networks, we’re united by a shared mission...  ...from the office full time, with flexibility when...  ...Career As a Design Verification engineer on the ASIC team, you will ensure...  ..., national origin, physical or mental disability...  ...Santa Clara, United States of AmericaType: Full... 
    Full time
    Casual work
    Work at office

    Palo Alto Networks

    Santa Clara, CA
    1 day ago
  • $100k

     ...Tenstorrent is looking for a Physical Design CPU Methodology Engineer who defines and drives...  ...remote based out of the United States. We welcome candidates at...  ...Engineer with 10+ years of ASIC/SoC/CPU experience,...  ...implementation and signoff, including timing closure, power... 
    Full time
    Remote work

    Tenstorrent

    Santa Clara, CA
    27 days ago
  • $139k - $295k

    ## Senior Memory Design EngineerSan Jose, California, United States of AmericaApply NowFind out how well you match with...  ...motivated **Senior Memory Design Engineer** to join our Memory Design team....  ...estimates it could pay for this full-time position is:$139,000.00 - $295,00... 
    Full time
    Local area
    Immediate start

    Jobleads-US

    San Jose, CA
    3 days ago
  • $194.6k - $285.7k

     ...performance Silicon ASICs. Our silicon...  ...IC package design and...  ...Routing Hardware Engineering team develops...  ...innovation across the full product...  ...business units and engineering...  ...together across the physical and digital...  ...periods of time.U.S....  ...by specific state, are listed below... 
    Full time
    Contract work
    Temporary work
    Work at office
    Local area
    Flexible hours
    Shift work

    CISCO Systems

    Milpitas, CA
    2 days ago
  • $198.7k - $298.1k

     ...Technologies, Inc.## Job Area:Engineering Group, Engineering...  ...in the world to create designs that push the envelope...  ...develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer,...  ...handling,* Knowledge of ASIC back-end design flows... 
    Work experience placement
    Work from home

    Jobleads-US

    Santa Clara, CA
    1 day ago
  • $167k - $275k

     ...GlobalFoundries is a leading full-service...  ...combination of design, development,...  ...Digital Design Engineer will lead the...  ...verification, physical design, DFT,...  ...memory management units (MMU),...  ...Support synthesis, timing closure, low-power...  ...specified by local, state or federal law... 
    Full time
    Local area

    Globalfoundries

    Santa Clara, CA
    2 days ago
  • $186.9k - $267.7k

     ...grow. Because full product development—from design to...  ...RTL to meet timing and performance...  ...Mentor junior engineers on performing...  ...closely with physical design team to...  ...8+ years of ASIC Design experience...  ...restricted stock units, which vest following...  ...by specific state, are listed... 
    Full time
    Temporary work
    Local area
    Flexible hours

    CISCO Systems

    San Jose, CA
    4 days ago
  •  ...this leadership role, you will lead ASIC front-end physical design and associated engineering workflow development for...  ...aspects at both the block level and full-chip within a fast-paced, agile HPC...  ...level and knowledge of full chip timing analysis ~ Excellent analytical... 
    Full time
    Remote work
    Flexible hours

    Jobleads-US

    Sunnyvale, CA
    2 days ago
  • $156.4k - $253k

     ...Alto Networks®, we’re united by a shared mission—...  ...work from the office full time, with flexibility when...  ...the Role Join our ASIC team and help deliver...  ...You will own module design from specification through...  ...verification and physical‑design engineers to hit aggressive... 
    Full time
    Work at office

    Jobleads-US

    Santa Clara, CA
    3 days ago
  •  ...advancements. Responsibilities: Lead ASIC front-end physical design and engineering workflow development for generative...  ...physical design at both block and full-chip levels. Drive optimization,...  .... Provide guidance for static timing analysis (STA) and contribute to... 
    Full time

    Anysilicon

    Sunnyvale, CA
    1 day ago
  • $143.8k - $230k

     ...If you are a first time user, please...  ...Principal Digital Design Engineer to serve as the Chip...  ...microarchitecture, and full chip integration....  ...analog design, physical design, and verification...  ...experience in ASIC/SoC digital design...  ...protected by federal, state, or local law. We... 
    Full time
    Local area

    Broadcom

    San Jose, CA
    4 days ago
  • $163k - $236k

    Participate in the physical design of complex blocks....  ...closure of the full chip and individual...  ...degree in Electrical Engineering, Computer...  ...place and route, and timing closure).Experience...  ...Tensor Processing Unit) technology that powers...  ...systems.As an ASIC Physical Design Engineer... 
    Worldwide

    Google

    Sunnyvale, CA
    2 days ago
  • $213k - $287.5k

    Annapurna Labs designs silicon and software that accelerates...  ...unimaginable a short time ago—even yesterday....  ...We’re looking for an ASIC Physical Design Engineer to help us trail-...  ...follow all federal, state, and local laws and...  ...and restricted stock units (RSUs). Final... 
    Local area
    Flexible hours

    Amazon

    Cupertino, CA
    1 day ago
  • $136k - $218.5k

     ...looking for a top-notch ASIC engineer to join the team. The...  ...with the front design team to understand the...  ...team to help craft the physical floorplan of the chip....  ...Optimization and Ease of timing closure to innovate and...  ...US, CA, Santa Clara; US, TX, AustinType: Full time
    Full time
    Work experience placement

    Nvidia

    Santa Clara, CA
    4 days ago
  • $136k - $218.5k

     ...NVIDIA is looking for an Senior ASIC Design Engineer to join our Memory Subsystem...  .../formal verification/physical design team to deliver a world...  ...including RTL design, synthesis and timing analysis using innovative...  ...by law.SummaryLocation: US, CA, Santa ClaraType: Full time
    Full time

    Nvidia

    Santa Clara, CA
    1 day ago
  • $129.4k - $207k

     ...Note:1. If you are a first time user, please create your candidate...  ...Broadcom is searching for a Physical IC Design Engineer to join the Data Center...  ...characteristic protected by federal, state, or local law. We will also...  ...USA-California-San Jose-1320 Ridder Park DriveType: Full time
    Full time
    Local area
    Remote work

    Broadcom

    San Jose, CA
    1 day ago
  • $122.44k - $232.19k

     ...every single day to design and manufacture...  ...in Electrical Engineering, Computer Engineering...  ...internships or full-time employment Or a PhD...  ...of the CMOS ASIC design flow.Job Type...  ...HireShift:Shift 1 (United States of America)...  ..., ancestry, age, physical or mental disability... 
    Full time
    Internship
    Local area
    Immediate start
    Shift work

    Intel

    Santa Clara, CA
    23 hours ago
  • $196k - $310.5k

     ...are now looking for a Senior ASIC Floorplan Design Engineer!NVIDIA is seeking a...  ...architects, design leads, physical design leads and package leads...  ...improvement opportunitiesSolve timing and routing congestion issues...  ...: US, CA, Santa Clara; US, TX, AustinType: Full time
    Full time

    Nvidia

    Santa Clara, CA
    3 days ago
  • $171.6k - $245k

     ...the TeamAcacia designs intelligent...  ...mixed-signal engineers to collaborate...  ...into the ASIC. In addition,...  ...together across the physical and digital...  .... The full salary range...  ...restricted stock units, which vest following...  ...periods of time.U.S....  ...by specific state, are listed below... 
    Full time
    Temporary work
    Work at office
    Local area
    Flexible hours
    3 days per week

    CISCO Systems

    San Jose, CA
    1 day ago

Do you want to receive more vacancies?

Subscribe and receive similar vacancies to ASIC Physical Design Engineer II (Full Time) - United States. Be the first to apply!