Senior ASIC Physical Design Engineer
Anysilicon
Tensordyne, a leading AI system solution company, specializes in high-performance, low-power generative AI inference systems. With a mission to accelerate multimodal generative AI inference at scale, Tensordyne is at the forefront of innovation in AI technology. The company, headquartered in Sunnyvale, CA, and Munich, Germany, offers a supportive work environment with comprehensive benefits and competitive compensation, aiming to build a healthy and motivated team to drive technological advancements.
Responsibilities:
- Lead ASIC front-end physical design and engineering workflow development for generative AI inference products.
- Guide and assist colleagues in improving frontend physical design at both block and full-chip levels.
- Drive optimization, implementation, and exploration of new frontend physical design workflows, including synthesis, formal checks, and power analysis.
- Provide guidance for static timing analysis (STA) and contribute to the full ASIC chip design process.
- Innovate and improve scalable, reliable, high-performance systems and tools for next-generation products.
- Collaborate closely with ASIC team members to understand and enhance their workflows and EDA needs.
Qualifications:
- 10 years of hands‑on ASIC engineering experience with deep knowledge of VLSI/SoC chip physical design workflows.
- Experience with EDA tools like Cadence/Synopsys (Genus/DC), power analysis, and clock methodology.
- Strong physical design knowledge for front-end optimization using standard EDA tools.
- Experience leading backend design teams with understanding of clock trees, routing, DRC, LVS, and metal fill until artwork release.
- Understanding of STA analysis and constraints for block level and full chip timing analysis.
- Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or a related technical field.
Skills:
- Excellent analytical, written, and verbal interpersonal skills.
- Ability to collaborate productively within a global engineering team in a fast‑paced startup environment.
- Strong problem‑solving skills with a focus on designing, debugging, and optimizing EDA solutions.
$136k - $218.5k
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Job Title: Senior ASIC Design EngineerJob Location: Santa Clara, CA or Boston, MACompensation: $150K - $250K base DOE plus equityRequirements... ...OverviewWe are seeking a highly skilled Senior ASIC Design Engineer to lead the design and development of advanced ASIC...Senior- ...ROLE: You will contribute to the ASIC (chip) design for high-performance network chips... ...the architecture, IP design, Physical Design teams, and product engineers to achieve first pass silicon success... ...candidate will work with senior silicon design engineers. The candidate...Senior
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...global leader whose innovative designs are pushing the boundaries of... ...both hardware and software engineers to identify and address the unique... ...policy.What You’ll DoOwn the physical implementation of memory-... ...timing closure — for complex ASIC/SoC designs.Proficiency with...SeniorWork at officeFlexible hoursNight shift$250.6k - $362.6k
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