Design Verification Engineers DDR

OverviewRAPS Consulting Inc, headquartered in NJ, is one of the nation's fastest-growing staffing companies. Our mission is to help companies identify the right resources at the right time and cost by building strong relationships with clients and candidates. We specialize in making the best matches through contract, full-time, or payroll services, with a team of qualified and experienced hiring professionals dedicated to this mission.PositionDesign Verification Engineers DDR (either IP or SoC level experience)Experience – 10+ YearsLocation: US RemoteFull TimeResponsibilitiesDefine and implement verification strategies and test plans for DDR memory interface designsDevelop UVM/SystemVerilog-based testbenches and reusable verification componentsPerform protocol-level verification for DDR memory interfaces and validate complianceCollaborate with architecture, RTL, and system teams to understand design intent and corner casesOwn functional coverage, regression setup, and closureIntegrate DDR models, controllers, PHYs, and validate their interactionsDebug and resolve simulation failures and functional issuesDrive code and functional coverage improvements to ensure thorough verificationLead or participate in technical reviews and mentor junior engineersRequired Skills10+ years of hands-on experience in ASIC/IP/SoC verificationStrong expertise in SystemVerilog, UVM, and functional coverage methodologyIn-depth understanding and working experience with DDR3/DDR4/DDR5/LPDDR protocolsExperience with DDR controllers, PHY integration, and JEDEC standardsProficient in simulation and debug tools such as Synopsys VCS, Cadence Xcelium, QuestaSim, etc.Good scripting skills in Python, Perl, or Shell for automation and regression managementExcellent debugging and problem-solving skillsFamiliarity with AXI/AHB protocols and interconnects is a plusExperience working with memory models and timing analysisPreferred QualificationsExperience with post-silicon validation or DDR hardware bring-upKnowledge of formal verification tools and techniquesExperience with low power verification and timing closure toolsJob DetailsSeniority level: Mid-Senior levelEmployment type: Full-timeJob function: Engineering and Information TechnologyIndustries: IT Services and IT ConsultingJ-18808-Ljbffr