Principal Analog IC Design Engineer, High Speed SerDes

Responsibilities The Principal Analog IC Designer is responsible for the design and development of analog/mixed-signal IC circuit blocks from initial concept/specification through final verification of conformance to customer specifications. Qualifications Minimum 7 years of experience in CMOS SerDes or high-speed I/O IC design and development. Working knowledge of common SerDes standards and their electrical requirements is a plus. Thorough understanding of jitter and signal equalization techniques. Proficient design experience in SerDes circuit blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low-jitter PLL, High Speed Clock Distribution, ADC and DAC, Bias and Bandgap, and Voltage Regulators. Excellent problem‑solving skills, analog aptitude, good communication skills, and ability to work cooperatively in a team environment. Proficiency in using CAD tools for circuit simulation, layout, and physical verification. Cadence tool experience, lab test experience, and design experience at >10Gbps and in MS or PhD in EE. Compensation & Benefits Annual salary range for California: $136,500 to $253,500. Eligible for incentive compensation (bonus, equity) and benefits. Benefits include paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, and a variety of medical, dental and vision plan options. Equal Employment Opportunity Cadence is committed to equal employment opportunity throughout all levels of the organization and considers all qualified applicants without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, veteran status, disability, or any other protected class. Legal Notice Cadence participates in the E-Verify program in certain U.S. locations as required by law. #J-18808-Ljbffr