Senior STA Engineer - Lead Timing for 7nm/5nm/3nm
Synopsys, Inc.
Synopsys, Inc. is seeking a Principal Engineer to drive timing sign-off methodologies and tackle complex challenges in advanced-node SoC development. You will own full-chip and block-level STA sign-off, ensuring successful tapeouts while collaborating with cross-functional teams. Ideal candidates will have 10–15+ years of experience, deep expertise in static timing analysis, and a proven track record with advanced nodes. You will also mentor junior engineers and influence architectural decisions, contributing to silicon design innovations. #J-18808-Ljbffr Synopsys, Inc.
Vacancy posted 3 days ago
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