Senior ASIC Power Engineer - LPU

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing, where our GPU acts as the brains of computers, robots, and self‑driving cars that can understand the world. As an NVIDIA employee, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. As a Senior ASIC Power Engineer in our Santa Clara, CA office, you will play a meaningful role in crafting the power architecture of our world-class products. Responsibilities Join the NVIDIA Power Architecture Group handling the full range of power‑related activities including ASIC energy evaluation, power architecture, low‑power development, power‑aware verification, advanced power methodologies, UPF methodologies, power‑feature bring‑up on silicon, and post‑Si power correlation for NVIDIA's product lineup. Support power analysis efforts by aiding in the architecture, creation, verification, and correlation of power estimation models/tools for NVIDIA's products. Be part of the team that architects and builds system‑level power features for optimizing dynamic and leakage power dissipation for different use cases. Work on power verification which includes structural, functional, and power‑aware verification of power features of NVIDIA products by developing test plans, writing test cases, building test‑bench components like monitors, assertions, and coverage points, and owning verification convergence across RTL, Gates, and Silicon. Validate the efficiency of the power features on silicon, conduct studies, and contribute to Performance/Watt improvement ideas. Help develop power management solutions and foster innovation in energy efficiency throughout NVIDIA's product portfolio. Qualifications B.Tech./M.Tech (or equivalent experience) with over 5 years of experience in power analysis, power development, power‑aware verification, UPF methodologies, and power correlation. Solid understanding of all power aspects, including full‑chip power modeling, transistor‑level leakage and dynamic characteristics in VLSI circuits. Strong fundamentals in digital build flow and Verilog (especially low‑power RTL development). Familiarity with low‑power build techniques such as multi‑VT, clock gating, power gating, voltage islands, and Dynamic Voltage‑Frequency Scaling (DVFS). Solid experience in power estimation methods, processes, and algorithms. Working experience with scripting languages like Python is a must. Prior experience writing software‑driven power verification tests and silicon debug is necessary. Experience in power supply and supply noise analysis and reduction is advantageous. Must be an excellent collaborator and prepared to work with international groups from varied cultural origins in a dynamic environment. Ways to Stand Out Good debugging and problem‑solving skills. Strong communication abilities and the capability to work well with others. Solid programming skills, ideally in C++ and Python. Knowledge of lab equipment for power measurements, including oscilloscopes or DAQs, and the capability to troubleshoot board‑level power issues is a plus. Benefits Competitive base salary ranging from 136,000 USD to 218,500 USD for Level 3, and 168,000 USD to 264,500 USD for Level 4. Equity and benefits are also provided. Additional benefits and information are available at Applications for this job will be accepted at least until April 12, 2026. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. We do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law. #J-18808-Ljbffr NVIDIA Gruppe