Senior SoC Compute/Memory Subsystem Architect (Folsom)

Job Details:Job Description: About the RoleThe CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high-performance networking silicon. Our team architects next-generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency. We specialize in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies that form the backbone of modern distributed computing systems.We are seeking a Senior SoC Compute/Memory Subsystem Architect to define and drive the architecture of compute complexes and high-performance memory subsystems for next-generation IPU/DPU platforms.This role is responsible for end-to-end architecture of CPU clusters, cache hierarchies, coherency models, and memory subsystems. You will optimize system-level performance, scalability, power efficiency, and programmability while ensuring seamless interaction with networking, storage, and accelerator subsystems in hyperscale environments.What You’ll DoKey responsibilities will include but not limited to:Compute Subsystem Architecture1. Define architecture for IPU compute complexes (e.g., ARM/x86 clusters), including core selection, scaling strategy, and configuration tradeoffs2. Architect compute subsystem roles (control plane, data plane assist, offload execution, management services)3. Drive compute architecture decisions balancing performance, power, and areaCache Hierarchy and Coherency Architecture1. Define and evolve multi-level cache hierarchy (private/shared caches, system-level cache)2. Architect coherency models across compute cores, accelerators, and IO subsystems (coherent vs non-coherent interactions)3. Evaluate tradeoffs between latency, bandwidth, scalability, and coherence domain complexityMemory Subsystem Architecture1. Architect system memory subsystems including:DDR / LPDDR interfacesMemory controllers and scheduling policiesBandwidth provisioning and scaling strategies2. Work with Performance architect in define memory access models for compute, network, and accelerator subsystems3. Ensure optimal balance between latency-sensitive control workloads and bandwidth-intensive datapath workloadsIO Memory and Virtualization Architecture (SMMU/IOMMU)1. Define architecture for SMMU/IOMMU supporting virtualization-heavy IPU workloads2. Architect features such as:Multi-tenant isolation and security boundariesShared vs isolated memory models3. Ensure efficient interaction between host, IPU/DPU compute, and offload enginesSystem-Level Integration (Compute Network Storage)1. Architect integration between:Compute subsystemNetwork subsystem (packet processing pipelines)Storage and accelerator subsystems2. Optimize data movement across subsystems to minimize copies, latency, and bandwidth overhead.3. Drive system architecture decisions for balanced SoC performance.Power, Efficiency, and Scaling Strategy1. Define compute and memory strategies for power efficiency and DVFS scalability.2. Architect mechanisms for:Memory bandwidth throttling / prioritizationPer-subsystem scaling3. Optimize performance-per-watt at system level.Multi-Generation Architecture Roadmap1. Lead long-term roadmap for compute and memory evolution across IPU/DPU product generations2. Define scaling strategies for:Core count and frequencyMemory bandwidth and capacityCache scaling and topology3. Ensure backward compatibility and smooth migration across product linesCross-Functional Leadership1. Collaborate with teams across:Networking subsystem (NSS)SoC fabric/interconnectFirmware, OS, and driversValidation and performance modeling and testing2. Drive architecture alignment and resolve cross-domain tradeoffBehavioral traits that we are looking for: (soft skills that you would like to see in a candidate)Strategic thinker: Ability to define long-term architecture vision and align stakeholdersTechnical leadership: Influences across teams without direct authorityProblem solver: Approaches complex system challenges with structured thinkingCollaboration: Builds strong partnerships across engineering disciplinesCustomer-focused mindset: Translates real-world workload needs into solutionsAdaptability: Navigates ambiguity and evolving technical requirementsOwnership mindset: Drives initiatives from concept through executionIntel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life. See Intel Benefits for more details. Qualifications:You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Note: For information on Intel’s immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship InformationMinimum Qualifications and Experience:Batchelor's degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of Study.You must have 7 + years of experience in the following:SoC / CPU / memory subsystem architectureCPU architecture and cache hierarchiesMemory subsystems (DDR/HBM, controllers, QoS)Coherent/Non-Coherent interconnect architecturesExperience in system-level performance and PPA tradeoff analysisDrive architecture definition from concept to siliconPreferred Qualifications and Experience:Post Graduate degree in Electrical Engineering, Computer Engineering, or in a STEM related Field of StudyARM and x86 compute and memory subsystem experience, including NUMA systems, cache coherency, or large scale platform architectures.Experience with IPU / SmartNIC or accelerator centric SoCs, particularly in cloud and hyperscale environmentsFamiliarity with PCIe, CXL, and memory semantics for high performance IO.Track record of multi generation architectural ownership and mentoring other architects.Join us in building a brighter future through technology innovation!Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, Santa ClaraAdditional Locations:US, Arizona, Phoenix, US, California, Folsom, US, California, San Jose, US, Colorado, Fort Collins, US, Texas, AustinBusiness group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.The application window for this job posting is expected to end by 07/31/2026*ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.SummaryLocation: US, California, Santa Clara; US, Colorado, Fort Collins; US, California, Folsom; US, Texas, Austin; US, Arizona, Phoenix; US, California, San JoseType: Full time