Senior SoC Network Subsystem Architect (Folsom)

Job Details:Job Description: About the RoleThe CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high-performance networking silicon. Our team architects next-generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency. We specialize in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies that form the backbone of modern distributed computing systems.We are seeking a Senior SoC Network Subsystem Architect to define and lead the architecture of high-performance network subsystems for next-generation IPU/DPU platforms. This role focuses on designing scalable, programmable networking pipelines that support hyperscale and cloud data center workloads.You will drive the end-to-end Network Subsystem (NSS) architecture, including packet processing pipelines, protocol engines, QoS frameworks, and observability features. This is a highly cross-functional leadership role requiring deep technical expertise and strong collaboration across hardware, software, and systems teams.What You’ll DoKey responsibilities will include but not limited to:Network Subsystem Architecture Definition1. Own end-to-end NSS architecture, including packet processing pipelines, protocol engines, and interface datapaths2. Architect high-performance packet pipelines supporting hundreds of millions of packets/sec throughput and processing flows3. Drive architectural direction for programmable vs. fixed-function pipeline balance and future extensibility4. Specify network subsystem pipeline scaling strategies and define multi-generation NSS architecture roadmap6. Lead design decisions for pipeline partitioning, feature scalability, and backward compatibilityQoS, Scheduling, and Flow Management1. Architect advanced scheduling frameworks (per-flow shaping, multi-level scheduling, traffic class isolation)2. Define QoS models to support multi-tenant workloads, virtualization, and service chainingDebug, Telemetry, and Observability1. Define architecture for telemetry, performance counters, and real-time observability of pipeline behavior2. Architecture support for field debug, failure triage, and large-scale deployment monitoringCross-Functional Leadership1. Collaborate across SoC, compute, memory, SW/FW, validation, and customer teams to drive architecture closure2. Interface with external customers to translate workload requirements into NSS architecture decisions3. Lead architectural reviews and influence cross-team technical directionBehavioral traits that we are looking for: Strategic thinker: Ability to define long-term architecture vision and align stakeholdersTechnical leadership: Influences across teams without direct authorityProblem solver: Approaches complex system challenges with structured thinkingCollaboration: Builds strong partnerships across engineering disciplinesCustomer-focused mindset: Translates real-world workload needs into solutionsAdaptability: Navigates ambiguity and evolving technical requirementsOwnership mindset: Drives initiatives from concept through executionIntel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life. See Intel Benefits for more details. Qualifications:Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Note: For information on Intel’s immigration sponsorship guidelines, please see Intel U.S. Immigration Sponsorship InformationMinimum Qualifications and Experience:Bachelor’s degree in Electrical/Computer Engineering, Computer Science or related degree with 7 + years of experience.You must have 7+ years of experience in the following: Networking ASIC / SoC / IPU / DPU architectureHigh-speed packet processing pipelinesExperience in system-level architecture tradeoffsDefine and deliver architecture for large-scale data center networking systemsPreferred Qualifications and Experience:Experience with programmable datapath architectures (P4, pipeline microcode, or hybrid models)Experience with AI/HPC scale-out networking and congestion control architecturesTransport protocols offloadsQoS, scheduling, and multi-tenant isolationFamiliarity with coherent or shared-memory offload models (e.g., CPU-IPU integration)Experience with hyperscaler deployments or customer co-design engagementsJoin us in building a brighter future through technology innovation!Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, Santa ClaraAdditional Locations:US, Arizona, Phoenix, US, California, Folsom, US, California, San Jose, US, Oregon, Hillsboro, US, Texas, AustinBusiness group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel. Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.Work Model for this RoleThis role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.*ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.SummaryLocation: US, California, Santa Clara; US, Oregon, Hillsboro; US, California, Folsom; US, Texas, Austin; US, Arizona, Phoenix; US, California, San JoseType: Full time