Physical Design Engineer (PnR / PPA / Timing Closure)
$100k - $180kWipro
Physical Design Engineer (PnR / PPA / Timing Closure) Job Description Job Title: Physical Design Engineer (PnR / PPA / Timing Closure) City: Austin, Mountain View State/Province: California, Texas Posting Start Date: 9/25/26 Wipro Limited (NYSE: WIT, BSE: 507685, NSE: WIPRO) is a leading technology services and consulting company focused on building innovative solutions that address clients’ most complex digital transformation needs. Leveraging our holistic portfolio of capabilities in consulting, design, engineering, and operations, we help clients realize their boldest ambitions and build future-ready, sustainable businesses. With over 230,000 employees and business partners across 65 countries, we deliver on the promise of helping our customers, colleagues, and communities thrive in an ever-changing world. For additional information, visit us at Job Description We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes. Key Responsibilities Drive block-level physical design implementation from netlist to GDSII. Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification. Optimize designs for Power, Performance, and Area (PPA) targets. Achieve timing closure across multiple corners and modes. Analyze and resolve setup, hold, transition, capacitance, and noise violations. Develop and maintain timing constraints (SDC) and STA signoff methodologies. Perform EMIR (Electromigration & IR Drop) analysis and closure. Collaborate with RTL, DFT, STA, and Signoff teams to ensure successful tapeout. Debug physical design issues and drive design convergence within project schedules. Required Skills Strong experience in Physical Design and PnR flow. Hands‑on expertise in: Floorplanning Placement & Optimization Clock Tree Synthesis (CTS) Routing Timing Closure Static Timing Analysis (STA) Timing Constraints (SDC) EMIR Analysis PPA Optimization Experience with industry-standard EDA tools such as: Synopsys Fusion Compiler / ICC2 PrimeTime Cadence Innovus (optional) RedHawk / Voltus (EMIR) Good understanding of low-power design techniques and signoff methodologies. Preferred Qualifications Bachelor's or Master's degree in Electrical/Electronics Engineering. Experience in advanced nodes (7nm/5nm/3nm preferred). Strong debugging and problem-solving skills. Experience working with cross-functional silicon teams. Mandatory Skills: VLSI Physical Place and Route.Experience: 8-10 Years. The expected compensation for this role ranges from $100,000 to $180,000 . Final compensation will depend on various factors, including your geographical location, minimum wage obligations, skills, and relevant experience. full range of medical and dental benefits options disability insurance paid time off (inclusive of sick leave) other paid and unpaid leave options Applicants are advised that employment in some roles may be conditioned on successful completion of a post-offer drug screening, subject to applicable state law. Wipro provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state, or local laws. Applications from veterans and people with disabilities are explicitly welcome. We are an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, caste, creed, religion, gender, marital status, age, ethnic and national origin, gender identity, gender expression, sexual orientation, political orientation, disability status, protected veteran status, or any other characteristic protected by law. Wipro is committed to creating an accessible, supportive, and inclusive workplace. Reasonable accommodation will be provided to all applicants including persons with disabilities, throughout the recruitment and selection process. Accommodations must be communicated in advance of the application, where possible, and will be reviewed on an individual basis. Wipro provides equal opportunities to all and values diversity. Reinvent your world. We are building a modern Wipro. We are an end-to-end digital transformation partner with the boldest ambitions. To realize them, we need people inspired by reinvention. Of yourself, your career, and your skills. We want to see the constant evolution of our business and our industry. It has always been in our DNA - as the world around us changes, so do we. Join a business powered by purpose and a place that empowers you to design your own reinvention. Information at a Glance Get Job Alerts Receive notifications when we have open roles and get other relevant career news Join Us Explore open rolesthat match your interests and skills If you encounter any suspicious mail, advertisements, or persons who offer jobs at Wipro, please email us at View email address on click.appcast.io . Do not email your resume to this ID as it is not monitored for resumes and career applications. Any complaints or concerns regarding unethical/unfair hiring practices should be directed to our Ombuds Group at View email address on click.appcast.io . © 2026 Wipro Limited #J-18808-Ljbffr Wipro
- Globex Digital Corp. seeks a Physical Design Engineer for Austin, TX to lead PnR/VLSI flow, floorplanning, CTS, routing, and timing convergence. You will optimize Power-Performance-Area (PPA) and ensure timing closure across multiple corners while addressing SETUP/HOLD...Suggested
- ...Description We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology... ...Area (PPA) targets. Achieve timing closure across multiple corners and modes....Suggested
- Wipro Limited in Austin, Texas is seeking a Physical Design Engineer with strong PnR, PPA optimization, and timing convergence to drive block-level design from netlist... ...floorplanning, CTS, routing, and timing closure across advanced nodes, collaborating with RTL/STA...Suggested
- She Jobs is seeking a Physical Design Engineer to lead block-level PD from netlist to GDSII in an... ...node environment. The role emphasizes PPA optimization, timing convergence, and close collaboration... ...experience in Physical Design and PnR, floorplanning, CTS, routing, and STA...Suggested
- Vaspire Technologies Inc. is seeking a Physical Design Engineer with strong PnR, PPA optimization, and timing convergence expertise for advanced nodes. You will drive block-level implementation from netlist to GDSII, perform floorplanning, placement, CTS, routing, and...Suggested
$100k
...looking for a mid- to senior-level Physical Design Engineer with a strong background in static timing analysis (STA). In this role,... ...of experience in STA, timing closure, and advanced-node design implementation... ...; experience with SPICE, PNR, placement, CTS, routing, post-...Permanent employment- ...SoC Physical Design Engineer, PnR Imagine what you could do here! At Apple, new ideas have a way of... ...collaborating with architecture, CAD, timing and logic design teams, with a critical... ..., and driving the signoff closure for the partitions. - Resolve and improve...Internship
- ...features. As a Staff Engineer Timing Methodology, you... ...our cutting-edge designs into silicon reality... ...aspects of timing closure from defining... ...achieve best in class PPA. Continuously... ...) Experience with PnR tools like Fusion... ...notified about new Physical Design Engineer jobs...Full timeSummer internship
$180.2k - $270.4k
...and Responsibilities As a Sr Staff Physical Design PPA Engineer. you will be responsible for... ...block through signoff flows, including timing and physical verification. You will... ...resolve design issues pertaining to block closure, providing feedback and working together...Hourly payFull timeRelocation- SoC Physical Design Engineer, PnR job at Apple Inc.. Austin, TX. We are seeking a seasoned Physical Design technical leader with deep expertise... ...focus area and are motivated to solve more challenging timing closure issues, area & power optimization etc. Minimum Qualifications...
$100k
...seniorities.Tenstorrent is seeking a talented Physical Design Engineer to implement high-performance blocks... ....Passionate about optimizing PPA through innovative implementation... ...with proven experience in synthesis, PnR, and timing closure on taped-out designs.Expertise with...Permanent employment$100k
...seniorities.Tenstorrent is seeking talented Physical Design Engineers to implement high-performance... ...MBIST).What we needExecute synthesis, PNR, and STA for assigned partitions of a... ...partitions end-to-end, including power intent, timing, and physical signoff in a modern...Permanent employment$136k - $218.5k
...on the world.We are now looking for a motivated Senior Physical Design and Timing Engineer to join our dynamic and growing team. If you want to challenge... ...development, and multi-mode, multi-corner timing closure factoring in process variations, IR drop, and Xtalk.Expertise...Full time$100k
...customers who need hardened, PPA-proven deliverables on... ...and foundry. This role owns physical implementation of those IP... ...end, from synthesis through PnR, timing closure, and GDSII signoff, and directly... ...You AreA hands-on physical design engineer who owns blocks end to end,...Permanent employment- ...experienced Digital Designer for SoC Implementation / Physical Design for... ...quality and meeting PPA targets.Key... ...and signoff.Drive timing, power, IR/EM, and... ...verification closure to achieve tapeout... ...Floorplanning, synthesis, PNR, CTS, routingSTA... .../ Electronics Engineering or related field...Full timeWork at officeLocal area
$108k - $172.5k
...and intelligence. We are now looking for a motivated ASIC Physical Design & Timing Engineer to join our multifaceted and growing team. If you are... ...all chips within NVIDIA. Drive physical design and timing closure of high-frequency and low-power hardware (CPUs, GPUs, SoCs...- Etched.ai, Inc. is seeking a Physical Design Engineer based in Austin, Texas. This role involves owning block-level implementation, driving timing closure, and collaborating with RTL designers to improve design processes. Candidates should have 5-10+ years in physical design...Work at office
- ...group, you’ll help design and manufacture our... ...a mix of strategic engineering along with hands‑on experience in physical design and large chip... ..., power and area (PPA). Work on... ...like top, STA, block PnR. Lead and resolve design... ...and all aspects of timing, electrical and physical...Temporary work
$200k - $300k
...Trading (HRT) is seeking a Physical Design Engineer with a broad, versatile skillset... ...-critical designs Close timing across multiple modes and... ...power, performance, and area (PPA) Diagnose and resolve... ...timing analysis and timing closure methodologies Expertise using...Work at officeLocal areaImmediate start- Xforia Global Talent & Technology Solutions is seeking an experienced Physical Design Contractor in Austin, TX to drive synthesis, floorplanning, and PPA optimization for large, timing-critical designs. You will work closely with RTL and external teams to ensure design...For contractors
- We are seeking an experienced engineer for SoC Static Timing Analysis for advanced semiconductor products... ...Static Timing Analysis across complex designs, driving initial constraints... ...from synthesis through final timing closure to close timing, including timing correlation...Full timeWork at officeLocal area
- ...impossible with GPUs, like real-time video generation models and... ...and staffed by leading engineers, Etched is redefining the... ...is looking for exceptional Physical Design engineers to join our team.... ...verification, drive timing closure and PPA optimization, supervise 3rd...Work at officeShift work
- ...hardware: frontier inference clusters. As a Physical Design Engineer, you will own block-level... ...GDSII sign-off, driving block-level timing closure and collaborating with RTL designers... ...You will supervise PD work, optimize PPA, and contribute to a fast-paced, startup...
$168k - $264.5k
...Developing innovative physical design methodologies for implementation... ...SOC, with emphasis on PPA (Power, Performance,... ...and turnaround time, while improving... ...Electrical or Computer Engineering (or equivalent experience... ...EM and IR analysis and closure Understanding of synthesis...$115.6k - $173.4k
...Team is actively seeking talented Physical Design Engineers to join our DSP PD team. As a Physical... ...and Power, Performance, and Area (PPA) optimization for advanced... ...MMMC clock-tree synthesis, routing Timing optimization and closure across multiple modes and corners...Work experience placement$239.6k - $324.1k
Annapurna Labs, designs custom silicon powering AWS’s cloud... ...looking for a Senior Manager, Physical Design Engineering to build and lead a world-... ...hierarchical methodology, PPA target-setting, and... ...hardest problems: multi-GHz timing closure, PDN architecture, high-speed...Local areaFlexible hours- ...future. Whether you’re designing next-gen processors,... ...world-class hardware physical design flow in a fast-... ...passion for solving complex engineering challenges and driving... ...for place-and-route, timing closure, power optimization,... ..., and area (PPA). Create and maintain...Worldwide
$185.2k - $250k
...responsibilities • Work with RTL/logic designers to drive architectural... ...-area tradeoffs for physical design closure • Drive IO/Core block... ...distribution, congestion analysis, timing closure, IR drop analysis,... ...with other physical design engineers as well as with the RTL/...Permanent employmentFlexible hours- Encore Semi, Inc. is seeking a Senior Physical Design Engineer to lead RTL-to-GDSII implementation of high-performance SoCs... ...will own advanced FinFET design challenges, push PPA boundaries, and drive robust timing closure targeting the GlobalFoundries 12LP node. You will...Remote job
$2,000 per month
...frontier intelligence. We co-design chips, racks, software... ...staffed by leading engineers, Etched is redefining... ...clusters. As a Physical Design Engineer, you will... ...Block-level & Subsystem PPA Optimization, and... ...GDSII. Drive block-level timing closure across all corners and...Work at officeRelocation packageShift work
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