ASIC Design Verification Engineer, Technical Leader

ASIC Design Verification EngineerThis role will work onsite out of our San Jose, CA office.The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco's core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms—like Silicon One—are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development—from design to qualification to production—is within our team, we're able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely with verification engineers, designers, hardware and cross-functional teams to verify the ASIC in simulation, in emulation, and during ASIC bring-up.Your Impact:Maintaining existing DV environments and enhancing themConstruct test bench including scoreboard, agents, sequencers, and monitors for new blocksWrite test plan, develop test cases, debug regression failures and drive to module verification closureEnsuring complete verification coverage through implementation and review of code and functional coverageUse AI tools to develop innovative methods and processes to improve quality of design verification.Minimum Qualifications:Bachelor's with 8+ years or Master's degree with 6+ of relevant experience required; prior experience with System Verilog and UVM methodologyPrior experience in verifying complex blocks, cluster, and/or top level for ASIC/SoCPrior experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes.Prior experience with functional coverage and constrained random DV environments.Scripting skills: Perl and/or Python scriptingPreferred Qualifications:Strong domain experience in one or more protocols is a plus – PCIe, CXL, Ethernet, AHB/AXI, DDR, MMU.Experience with Veloce/HAPS is a plusFormal verification (iev/vc formal) knowledge is a plus