Layout/Mask Designer 5 - VLSI Physical Design Engineer
Akaasa Technologies
Layout/Mask Designer 5 VLSI Physical Design Engineer
Location: Folsom, CA - ON-SITE
Contract Duration: 3+ Months
Interview: Virtual
Manager Notes
The hiring manager is specifically looking for candidates who clearly demonstrate 10+ years of relevant experience on their resumes.
Candidates with strong memory-controller, HBM, UCIe PHY, or AI data-center SoC experience are particularly desirable.
This is a very fast-filling position, so qualified candidates should be submitted as soon as possible.
Position Overview
We are seeking an experienced VLSI Physical Design Engineer to lead block-level physical design activities from RTL through GDSII for an advanced ASIC/SoC program in Folsom, CA.
This is a high-priority, fast-moving opportunity with strong potential for an immediate offer for qualified candidates.
Required Qualifications
- 10+ years of relevant VLSI/ASIC Physical Design experience .
- Strong hands-on experience with advanced process nodes .
- Extensive experience with Synopsys Fusion Compiler .
- Proven experience taking designs from RTL through GDSII .
- Strong understanding of physical design methodologies and design closure.
Preferred / Highly Desired Experience
Candidates with the following experience will stand out:
- Successfully closing physical design for memory controllers , particularly HBM memory controllers .
- Experience integrating PHY IP , especially UCIe PHY .
- Physical design experience on AI data-center SoCs .
- Experience with custom silicon or advanced accelerator designs, such as:
- NVIDIA GPU
- Broadcom AI accelerators
- Google custom/in-house silicon
- Meta custom/in-house silicon
- Similar high-performance AI/compute SoC platforms
Vacancy posted 2 days ago
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