GPU Power & RTL Design Engineer — SoC/IP Integration
The Briefed
Apple in Austin is seeking a senior RTL engineer to design and optimize RTL for GPU power management and SoC interface logic. You will collaborate with Platform Architecture, Software, Design Verification, and Physical Design teams to deliver RTL and specifications, integrate IP, and drive performance, power, and area goals across multi-site teams. The role requires a BS in EE, CE, or ECE, strong Verilog/SystemVerilog RTL experience, and scripting skills. #J-18808-Ljbffr The Briefed
Vacancy posted 2 days ago
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