Senior Front-End Design Architect: RTL/SoC IP Leader
Cadence
Cadence in Austin, Texas seeks an experienced Front End Design engineer to lead projects in the semiconductor industry. The role involves technical leadership, RTL development, and collaboration with cross-functional teams. Ideal candidates have over 10 years of experience in design and/or verification, including expertise in Verilog, project management, and IP integration. Competitive compensation and growth opportunities are offered. #J-18808-Ljbffr Cadence
Vacancy posted 1 day ago
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