Sr. Design Verification Engineer

Senior Design Verification Engineer – Complex SoC

Engagement: Contract, 6–9 months with potential extension

Location: 100% Remote

Geography: USA preferred; highly qualified candidates in other locations will be considered

Position Overview

We are seeking an exceptionally strong Senior Design Verification Engineer to support the verification of a highly complex, advanced SoC.

This is a hands-on technical role for an experienced verification engineer who can architect, develop, and enhance sophisticated UVM-based verification environments and testbenches . The ideal candidate has spent significant time verifying complex SoCs and SoC subsystems and is comfortable working independently on challenging verification problems.

This is not a junior or primarily test-execution position. We are looking for an engineer capable of developing verification infrastructure and testbenches for large, complex designs.

Required Qualifications

• 10–15+ years of Design Verification experience
• Exceptional expertise in SystemVerilog and UVM
• Extensive hands-on experience developing UVM testbenches and verification environments from the ground up
• Strong experience verifying highly complex SoCs and SoC subsystems
• Demonstrated ability to develop scalable verification architectures, including:
• UVM agents, drivers, monitors, sequencers, and scoreboards
• Reference models and checkers
• Functional coverage models
• Constrained-random stimulus
• Assertions and protocol checking
• Strong experience with SoC-level and subsystem-level verification
• Deep understanding of verification planning, test development, coverage closure, regression analysis, debugging, and root-cause analysis
• Ability to debug complex interactions across multiple IP blocks, interfaces, clocks, resets, and system-level scenarios
• Strong understanding of common SoC architectures, interfaces, memory systems, interconnects, and peripheral subsystems
• Ability to work independently in a distributed, remote engineering environment

Highly Desired Experience

Hands-on verification experience with one or more of the following is highly desirable:

• PCI Express (PCIe), preferably Gen5 or later
• UCIe
• High-speed Ethernet
• Complex SoC interconnect and subsystem verification
• Multi-core or heterogeneous SoC architectures
• High-speed interfaces and protocol verification

Ideal Candidate

The ideal candidate is a deeply technical verification engineer who has worked on large, sophisticated semiconductor designs and understands the challenges associated with verifying interactions across multiple SoC subsystems.

We are particularly interested in engineers who have taken ownership of major portions of a verification environment—not simply maintained existing tests—and who can quickly understand an unfamiliar architecture, identify verification requirements, and build robust UVM infrastructure to verify it.

This role requires someone who can operate with a high degree of technical independence while collaborating effectively with RTL designers, architects, verification engineers, and other members of a geographically distributed engineering team.

Engagement Details

• 6–9 month initial contract
• Potential for extension based on project requirements and performance
• 100% remote
• USA-based candidates strongly preferred
• Exceptional candidates in other locations will also be considered