HBM SoC Physical Design Engineer

Role Summary As a SoC Physical Design Engineer in the Heterogeneous Integration Group (HIG), you will drive the implementation of advanced HBM SoC logic/base die designs from netlist to GDSII, working closely with RTL design, verification, DFT, IP providers, packaging/assembly, and manufacturing teams to deliver best‑in‑class PPA and robust signoff collateral for tape‑out. Key Responsibilities Own physical implementation for SoC blocks and/or top‑level, including floor‑planning, placement, CTS, routing, and physical optimization. Drive timing closure across multi‑mode/multi‑corner scenarios; partner with RTL, architecture, and STA/signoff to converge designs. Integrate and implement complex IP (e.g., controllers, microcontrollers, NOC, interfaces, MBIST/DFT logic, buffers, PHY‑adjacent logic) with focus on robust physical integration and timing/power integrity. Perform or coordinate physical signoff, including DRC/LVS, IR drop/EM, and timing signoff, addressing violations efficiently. Partner with DFT teams to ensure scan/MBIST requirements are physically realizable and do not compromise PPA or schedule. Work with packaging, assembly, test, probe, and manufacturing collaborators to ensure builds meet manufacturability and quality requirements. Support tape‑out execution (checklists, ECO flows, signoff reviews) and contribute to post‑silicon debugging by correlating silicon behavior with PD/STA/power analysis. Identify flow gaps and improve productivity through scripting/automation and best‑practice methodology development. Required Qualifications Strong experience in SoC physical design implementation from netlist to GDSII on advanced nodes and complex designs. Proficiency with industry EDA tools (e.g., Cadence Innovus/Tempus, Synopsys ICC2/PrimeTime, Siemens Calibre). Solid understanding of STA fundamentals, clocking, constraints (SDC), and common closure techniques. Experience with power intent and power delivery considerations (e.g., UPF/CPF concepts, power grid planning, power gating). Familiarity with physical verification/signoff concepts: DRC, LVS, ERC, parasitic extraction awareness, and signoff handoff quality. Preferred Qualifications Experience with HBM / DRAM adjacent SoC designs or memory‑subsystem‑heavy SoCs. Instructor or mentor experience with early‑career engineers. Bachelor’s or master’s degree in electrical engineering, computer engineering, or a related field. Minimum 10years of experience in a related field. Compensation US base salary range: $146,000.00 – $309,000.00 per year. Additional compensation may include benefits, bonuses, and equity. Salary is determined by role, level, location, and individual factors. Benefits Micron offers medical, dental, and vision plans, income protection, paid family leave, paid time‑off program, paid holidays, and other benefit programs to support employee well‑being and professional growth. Equal Employment Opportunity Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity, or any other factor protected by applicable federal, state, or local laws. #J-18808-Ljbffr 1000 Micron Technology, Inc.