Technical Lead, Front-End Power Optimization

Technical Lead, Power Analysis And Optimization

The Common Hardware Group (CHG) creates innovative hardware platforms central to the AI era, powering Cisco's core Switching, Routing, and Wireless products for organizations globally. Our innovations in silicon, optics, and hardware platforms like Silicon One are shaping the technology industry. We're a global team of creative experts, bringing our unique backgrounds and bold ideas to push boundaries and help each other grow. Because full product development from design to qualification to production is within our team, we're able to think differently, experiment more, and work quickly. Join us to power the future of the digital world.

The Technical Lead, Power Analysis and Optimization, is responsible for driving power efficiency from the microarchitecture level through to physical implementation. You will bridge the gap between RTL design and silicon power, ensuring our designs meet aggressive Power, Performance, and Area (PPA) targets. This role spans all phases of the front-end design cycle, combining deep technical expertise in power modeling with leadership in cross-functional coordination.

Key Responsibilities:

• Evaluate ultra-high-bandwidth packet switching microarchitecture through a first-principles approach.
• Map application-level network traffic patterns to microarchitectural structures to pinpoint power inefficiencies.
• Develop a comprehensive understanding of the relationship between RTL design choices and their downstream impact on silicon power.
• Evolve beyond standard clock gating by implementing RTL modifications informed by application-specific traffic flow analysis.
• Integrate physical-aware methodologies early in the design cycle to ensure RTL architecture is inherently aligned with physical implementation constraints.
• Develop comprehensive power vectors that accurately simulate production-level network switching workloads.
• Utilize power vectors to perform precise power analysis, focusing on optimizations, IR drop, and droop profiling to identify and mitigate high-activity switching regions.
• Partner with the Physical Design (PD) team to understand clock tree structure as well as other implementation choices and propose RTL enhancements accordingly.
• Facilitate structured reviews to confirm that proposed RTL enhancements remain physically viable and functionally verified.
• Conduct rigorous post-implementation analysis to verify that all physical optimizations successfully meet defined power targets.

Minimum Requirements:

• Bachelor's Degree in Electrical or Computer Engineering with 8+ years of experience or Master's Degree in Electrical or Computer Engineering with 6+ years of experience, PhD in Electrical or Computer Engineering with 3+ years of experience.
• Experience in RTL design, optimization, and power modeling.
• Experience performing power analysis using PrimePower RTL.

Preferred Qualifications:

• Experience in mapping application-level workloads to microarchitectural features to achieve measurable power reduction through RTL-level modifications.
• Experience in high-speed packet switching architectures.
• Experience with advanced FinFET process nodes (5nm, 3nm, or below).
• Experience with Tcl/Python scripting for automating power analysis and RTL optimization workflows.
• Experience to work across design, physical design and other power teams to solve complex power/performance challenges.
• Experience leading technical initiatives and facilitating cross-functional collaboration between design, physical design, and power analysis teams to meet PPA targets.